公开(公告)号：US10037914B2

公开(公告)日：2018-07-31

申请号：US15655920

申请日：2017-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L21/76895 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/7831

Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

公开(公告)号：US10727234B2

公开(公告)日：2020-07-28

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  Runshun Wang ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US09728454B1

公开(公告)日：2017-08-08

申请号：US15242611

申请日：2016-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L21/76895 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475

Abstract: The present invention provides a semiconductor structure, includes a substrate, a dielectric layer disposed on the substrate, a first gate structure and a second gate structure disposed in the dielectric layer, a hard mask disposed in the dielectric layer, where the hard mask covers a sidewall of the first gate structure, and covers the second gate structure, and a contact structure disposed in the dielectric layer. The contact structure at least crosses over the hard mask. The contact structure includes a first contact portion and a second contact portion. The first contact portion contacts the first gate structure directly, the second contact portion contacts the substrate directly, and the hard mask is disposed between the first contact portion and the second contact portion.

公开(公告)号：US20170358491A1

公开(公告)日：2017-12-14

申请号：US15655920

申请日：2017-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L21/76895 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/7831

Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

公开(公告)号：US20150303120A1

公开(公告)日：2015-10-22

申请号：US14256989

申请日：2014-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jubao Zhang ,  Xing Hua Zhang ,  Hong Liao

IPC: H01L21/66 ,  H01L23/522 ,  H01L21/78 ,  H01L23/00

Abstract: A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate.

Abstract translation: 公开了半导体封装结构的制造方法。 该方法包括：提供具有正面和背面的晶片; 在晶片中形成多个通硅通孔（TSV）和在TSV上的多个金属互连，其中金属互连从晶片的前侧露出; 执行监视步骤以从晶片的背面屏蔽TSV故障; 并将晶片接合到基板。

公开(公告)号：US20180151571A1

公开(公告)日：2018-05-31

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  RUNSHUN WANG ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US09754828B1

公开(公告)日：2017-09-05

申请号：US15200000

申请日：2016-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/7831

Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

公开(公告)号：US09607123B2

公开(公告)日：2017-03-28

申请号：US14598236

申请日：2015-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xing Hua Zhang ,  Chi-Fa Ku ,  Hong Liao ,  Ye Chao Li ,  Hui Yang

IPC: G06F17/50 ,  H01L23/58 ,  H01L21/66 ,  H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/10 ,  H01L27/06 ,  H01L23/00

CPC classification number: G06F17/5081 ,  H01L21/823871 ,  H01L22/34 ,  H01L23/10 ,  H01L23/528 ,  H01L23/562 ,  H01L23/58 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

公开(公告)号：US20160211187A1

公开(公告)日：2016-07-21

申请号：US14598236

申请日：2015-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xing Hua Zhang ,  Chi-Fa Ku ,  Hong Liao ,  Ye Chao Li ,  Hui Yang

IPC: H01L21/66 ,  H01L23/10 ,  H01L23/528 ,  G06F17/50

CPC classification number: G06F17/5081 ,  H01L21/823871 ,  H01L22/34 ,  H01L23/10 ,  H01L23/528 ,  H01L23/562 ,  H01L23/58 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

Abstract translation: 半导体监视装置包括基板，形成在基板上的模具密封环，形成在模具密封环下方的基板中的深n型阱，以及与模密封环电连接的监视装置。 监测装置形成在限定在基板上的划线区域中。 深n型井的宽度大于模具密封环的宽度。