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公开(公告)号：US20240243124A1
公开(公告)日：2024-07-18
申请号：US18110353
申请日：2023-02-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Yang , Shih-Min Lu , Chi-Sheng Tseng , Yao-Jhan Wang , Chun-Hsien Lin
IPC: H01L27/088 , H01L21/8234
CPC classification number: H01L27/088 , H01L21/823456
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.
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公开(公告)号：US20240006468A1
公开(公告)日：2024-01-04
申请号：US17876467
申请日：2022-07-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Hsing Lee , Chun-Hsien Lin , Chih-Wei Yang
Abstract: A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.
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公开(公告)号：US20220392905A1
公开(公告)日：2022-12-08
申请号：US17363015
申请日：2021-06-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Hsing Lee , Chun-Hsien Lin , Chih-Wei Yang , Chang-Chien Wong , Te-Wei Yeh , Sheng-Yuan Hsueh
IPC: H01L27/112
Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.
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公开(公告)号：US11205710B2
公开(公告)日：2021-12-21
申请号：US16357333
申请日：2019-03-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Chien Hsieh , En-Chiuan Liou , Chih-Wei Yang , Yu-Cheng Tung , Po-Wen Su
IPC: H01L29/66 , H01L27/088 , H01L21/8234 , H01L21/265 , H01L21/266 , H01L29/78
Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
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公开(公告)号：US10818660B2
公开(公告)日：2020-10-27
申请号：US16407188
申请日：2019-05-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang
IPC: H01L27/088 , H01L21/762 , H01L29/66 , H01L21/8234 , H01L29/78
Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
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公开(公告)号：US10522415B1
公开(公告)日：2019-12-31
申请号：US16562454
申请日：2019-09-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang
IPC: H01L27/088 , H01L21/8234 , H01L29/08 , H01L29/06 , H01L27/12 , H01L21/84 , H01L29/66 , H01L21/82
Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.
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公开(公告)号：US10453849B2
公开(公告)日：2019-10-22
申请号：US15936396
申请日：2018-03-26
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC: H01L29/02 , H01L27/108 , G11C11/401
Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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公开(公告)号：US10283413B2
公开(公告)日：2019-05-07
申请号：US15264590
申请日：2016-09-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang
IPC: H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L21/84 , H01L27/12 , H01L29/66 , H01L21/82
Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.
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公开(公告)号：US10164039B2
公开(公告)日：2018-12-25
申请号：US15283445
申请日：2016-10-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Chih-Wei Yang , Yu-Cheng Tung
IPC: H01L29/76 , H01L29/423 , H01L29/66 , H01L21/28 , H01L29/49 , H01L21/768
Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.
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公开(公告)号：US10134629B1
公开(公告)日：2018-11-20
申请号：US15696267
申请日：2017-09-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Yen-Tsai Yi , Wei-Chuan Tsai , En-Chiuan Liou , Chih-Wei Yang
IPC: H01L21/44 , H01L21/768 , H01L29/78 , H01L23/532 , H01L23/535
Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.
