公开(公告)号：US09281201B2

公开(公告)日：2016-03-08

申请号：US14029824

申请日：2013-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/28176 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。

公开(公告)号：US09263257B2

公开(公告)日：2016-02-16

申请号：US14312707

申请日：2014-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/205 ,  H01L21/336 ,  H01L21/8232 ,  H01L29/08 ,  H01L29/16 ,  H01L29/43 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract translation: 公开了一种具有鳍状结构的半导体器件。 半导体器件包括：衬底; 基板上的鳍状结构; 以及在鳍状结构的顶表面和侧壁的一部分上的外延层，其中外延层和鳍状结构在其间包括锗浓度的线性梯度。

公开(公告)号：US09159831B2

公开(公告)日：2015-10-13

申请号：US13662561

申请日：2012-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

IPC: H01L21/70 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11

CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 电介质层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

公开(公告)号：US20140367779A1

公开(公告)日：2014-12-18

申请号：US13917623

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.

Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于空部分正下方的通孔。 门围绕着空的部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部形成空的部分，从而在通孔上形成空的部分。 形成围绕空闲部分的门。

公开(公告)号：US08884346B2

公开(公告)日：2014-11-11

申请号：US14156442

申请日：2014-01-15

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L29/786 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract translation: 半导体结构包括栅极结构，外延层和含碳硅锗覆盖层。 栅极结构位于衬底上。 外延层位于栅极结构旁边的衬底中。 含碳硅锗覆盖层位于外延层上。 否则，还提供了用于形成所述半导体结构的半导体工艺。

公开(公告)号：US08853740B2

公开(公告)日：2014-10-07

申请号：US13905148

申请日：2013-05-30

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US20140191285A1

公开(公告)日：2014-07-10

申请号：US14203581

申请日：2014-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

IPC: H01L29/165

CPC classification number: H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant. The epitaxial structures and the undoped cap layer include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The second semiconductor material in the epitaxial structure includes a first concentration and the second semiconductor material in the undoped cap layer includes a second concentration. The second concentration is lower than the first concentration, and is upwardly decreased.

Abstract translation: 具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。 外延结构包括掺杂剂。 外延结构和未掺杂的帽层包括具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料。 第二晶格常数大于第一晶格常数。 外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料包括第二浓度。 第二浓度低于第一浓度，并且向上减少。

公开(公告)号：US10141193B2

公开(公告)日：2018-11-27

申请号：US14949896

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

公开(公告)号：US10014227B2

公开(公告)日：2018-07-03

申请号：US14825165

申请日：2015-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

公开(公告)号：US09461150B2

公开(公告)日：2016-10-04

申请号：US14979594

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/36

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

Abstract translation: 公开了一种制造具有鳍状结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成鳍状结构; 在所述基板上形成第一电介质层和所述鳍状结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻第二介电层的一部分; 去除所述第一电介质层的一部分以暴露所述鳍状结构的顶表面和所述侧壁的一部分; 形成外延层以覆盖所述鳍状结构的暴露的顶表面和所述侧壁的一部分; 以及去除所述第二电介质层的一部分。