公开(公告)号：US11990518B2

公开(公告)日：2024-05-21

申请号：US17234731

申请日：2021-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US09728467B2

公开(公告)日：2017-08-08

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/302 ,  H01L29/788 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

公开(公告)号：US20240258378A1

公开(公告)日：2024-08-01

申请号：US18632253

申请日：2024-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US20220285500A1

公开(公告)日：2022-09-08

申请号：US17234731

申请日：2021-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US09478628B1

公开(公告)日：2016-10-25

申请号：US14853956

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Nien-Ting HO ,  Chi-Mao Hsu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Hsiang-Chieh Yen ,  Min-Chuan Tsai

IPC: H01L21/4763 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L29/66545

Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Abstract translation: 金属栅极形成工艺包括以下步骤。 第一金属层通过至少第一步骤和第二步骤形成在衬底上，其中第二步骤的处理能力高于第一步骤的处理能力。

公开(公告)号：US20240258379A1

公开(公告)日：2024-08-01

申请号：US18632275

申请日：2024-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure provides a semiconductor device, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US12027602B2

公开(公告)日：2024-07-02

申请号：US17093549

申请日：2020-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Feng Li ,  Chia-Hua Chang ,  Hsiang-Chieh Yen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/02293 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/7786

Abstract: A high electron mobility transistor (HEMT) is disclosed. The HEMT includes a substrate, a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, a third epitaxial layer disposed on the second epitaxial layer, and a gate disposed on the third epitaxial layer. An upper portion of the first epitaxial layer has a plurality of first recesses. The second epitaxial layer partially fills the first recesses and surrounding a plurality of first air slits in the first recesses.

公开(公告)号：US20170076995A1

公开(公告)日：2017-03-16

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract translation: 提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。 在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。 第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。 形成图案化的硬掩模层。 图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。 对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。 在第一气体处理中使用的气体包括含氮气体或含氧气体。

公开(公告)号：US20240322007A1

公开(公告)日：2024-09-26

申请号：US18675105

申请日：2024-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Feng Li ,  Chia-Hua Chang ,  Hsiang-Chieh Yen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/02293 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/7786

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a first epitaxial layer on the substrate, forming a plurality of first recesses in an upper portion of the first epitaxial layer, forming a second epitaxial layer on the first epitaxial layer and partially filling the first recesses to seal a plurality of first air slits in the first recesses, forming a third epitaxial layer on the second epitaxial layer, and forming a gate on the third epitaxial layer.

公开(公告)号：US20240313087A1

公开(公告)日：2024-09-19

申请号：US18675098

申请日：2024-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Feng Li ,  Chia-Hua Chang ,  Hsiang-Chieh Yen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/02293 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/7786

Abstract: A high electron mobility transistor includes a substrate having a continuous planar front surface, a first epitaxial layer directly and continuous disposed on the continuous planar front surface of the substrate, a plurality of first recesses arranged in an upper portion of the first epitaxial layer, a second epitaxial layer directly disposed on the first epitaxial layer and partially filling the first recesses and surrounding a plurality of first air slits in the first recesses, a third epitaxial layer disposed on the second epitaxial layer, and a gate disposed on the third epitaxial layer.