公开(公告)号：US20190164977A1

公开(公告)日：2019-05-30

申请号：US16226648

申请日：2018-12-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US20190074280A1

公开(公告)日：2019-03-07

申请号：US15951194

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou ,  Ting-Pang Chung ,  Chia-Wei Wu

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L27/10873 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02576 ,  H01L21/324 ,  H01L21/4814 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.

公开(公告)号：US20180211961A1

公开(公告)日：2018-07-26

申请号：US15877356

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Yung-Ming Wang ,  Ting-Pang Chung ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/60

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. Storage node contacts are formed on a semiconductor substrate including active regions. Each storage node contact contacts at least one of the active regions. Each storage node contact has a recessed top surface. A first distance exists between a topmost point and a lowest point of the recessed top surface in a vertical direction. A second distance exists between the topmost point and a bottom surface of the storage node contact in the vertical direction. A ratio of the first distance to the second distance ranges from 30% to 70%. The contact resistance between the storage node contact and other conductive structures formed on the storage node contact may be reduced by the storage node contact having the recessed top surface, and the electrical operation condition of the semiconductor memory device may be improved accordingly.

公开(公告)号：US20180182760A1

公开(公告)日：2018-06-28

申请号：US15464358

申请日：2017-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L27/10814 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02356 ,  H01L27/10852 ,  H01L28/40

Abstract: A dielectric structure and a manufacturing method thereof and a memory structure are provided. The dielectric structure includes a dielectric layer and a plurality of crystalline grains disposed in the dielectric layer. The dielectric layer includes a first high-K dielectric material with a first dielectric constant. Each crystalline grain includes a second high-K dielectric material with a second dielectric constant greater than the first dielectric constant and greater than 20. Each crystalline grain has a crystal structure, so that each crystalline grain has a third dielectric constant greater than the second dielectric constant. Whole dielectric constant of the dielectric structure can be raised by performing an annealing process to form the crystalline grains in the dielectric layer, and the capacity of the memory structure for storing electric charges can be increased.

公开(公告)号：US20180019324A1

公开(公告)日：2018-01-18

申请号：US15590510

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US20170294540A1

公开(公告)日：2017-10-12

申请号：US15095484

申请日：2016-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Cheng Hu ,  Kai-Hsiang Wang ,  Tien-I Wu ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/49 ,  H01L29/161 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.

公开(公告)号：US11770924B2

公开(公告)日：2023-09-26

申请号：US18106448

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H10B12/00 ,  H01L49/02

CPC classification number: H10B12/0387 ,  H01L28/60 ,  H10B12/0335 ,  H10B12/37 ,  H10B12/315

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

公开(公告)号：US20220271037A1

公开(公告)日：2022-08-25

申请号：US17741431

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

公开(公告)号：US10373958B2

公开(公告)日：2019-08-06

申请号：US15876216

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tsuo-Wen Lu ,  Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/10 ,  H01L29/49 ,  H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

公开(公告)号：US10332889B2

公开(公告)日：2019-06-25

申请号：US15951194

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou ,  Ting-Pang Chung ,  Chia-Wei Wu

IPC: H01L21/00 ,  H01L27/108 ,  H01L21/02 ,  H01L21/324 ,  H01L21/48 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.