公开(公告)号：US09281201B2

公开(公告)日：2016-03-08

申请号：US14029824

申请日：2013-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/28176 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。

公开(公告)号：US08853740B2

公开(公告)日：2014-10-07

申请号：US13905148

申请日：2013-05-30

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US09502244B2

公开(公告)日：2016-11-22

申请号：US15166291

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L21/76 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.

Abstract translation: 本发明提供一种形成半导体结构的方法，包括：首先提供衬底，然后进行第一干蚀刻工艺，以在衬底中形成凹陷。 之后，对凹部的底面执行离子注入工艺，然后执行湿蚀刻工艺，以蚀刻凹部的部分侧壁，从而分别在凹槽的两侧形成至少两个尖端，并且 进行第二干蚀刻工艺，以蚀刻凹部的部分底表面，其中在执行第二干蚀刻工艺之后，凹部的下部具有U形横截面轮廓。

公开(公告)号：US20160126091A1

公开(公告)日：2016-05-05

申请号：US14532015

申请日：2014-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chueh-Yang Liu ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02334 ,  H01L21/0206 ,  H01L21/02181 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.

Abstract translation: 氧化物的清洗方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域的基板上形成第一氧化物层。 在第一区域和第二区域的第一氧化物层上进行含有氢氧化铵（NH 4 OH）和过氧化氢（H 2 O 2）的工艺。 光致抗蚀剂层覆盖第一区域的第一氧化物层，同时暴露第二区域的第一氧化物层。 去除第二区域的第一氧化物层。 然后除去光致抗蚀剂层。

公开(公告)号：US20140256151A1

公开(公告)日：2014-09-11

申请号：US13784846

申请日：2013-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Sheng Chen ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Ted Ming-Lang Guo ,  Bo-Syuan Lee ,  Tsung-Hsun Tsai ,  Yu-Chin Cheng

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.

Abstract translation: 一种除去氮化硅材料的方法包括以下步骤。 提供了至少形成有栅极结构的衬底，并且在栅极结构的顶部上形成至少一个氮化硅硬掩模。 执行第一次去除以用第一磷酸（H 3 PO 4）溶液去除一部分氮化硅硬掩模。 随后进行第二次去除以用第二种磷酸溶液去除残留的氮化硅硬掩模。 第一次去除和第二次去除是原位进行的。 第二磷酸溶液的温度低于第一磷酸溶液的温度。

公开(公告)号：US20130288446A1

公开(公告)日：2013-10-31

申请号：US13928366

申请日：2013-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Ling-Chun Chou ,  Tsung-Hung Chang ,  Chun-Yuan Wu

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract translation: 公开了一种包括衬底和设置在衬底上的栅极结构的半导体结构。 栅极结构包括设置在基板上的栅极介质层，设置在栅极介电层上的栅极材料层和具有矩形横截面的外部间隔物。 外隔离物的顶表面比栅极材料层的顶表面低。

公开(公告)号：US20150303283A1

公开(公告)日：2015-10-22

申请号：US14279340

申请日：2014-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Ted Ming-Lang Guo

IPC: H01L29/66

CPC classification number: H01L29/66803 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes the following steps. A substrate including at least a fin layer and a plurality of gate electrodes is provided. A tilt and twist ion implantation is performed to form a plurality of doped regions in the fin layer. An etching process is performed to remove the doped regions to form a plurality of recesses in the fin layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供至少包括翅片层和多个栅电极的基板。 进行倾斜和扭转离子注入以在翅片层中形成多个掺杂区域。 执行蚀刻处理以去除掺杂区域以在散热片层中形成多个凹部。

公开(公告)号：US08883033B2

公开(公告)日：2014-11-11

申请号：US13784846

申请日：2013-03-05

Applicant: United Microelectronics Corp.

Inventor： Chi-Sheng Chen ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Ted Ming-Lang Guo ,  Bo-Syuan Lee ,  Tsung-Hsun Tsai ,  Yu-Chin Cheng

IPC: B44C1/22 ,  H01L21/302 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.

Abstract translation: 一种除去氮化硅材料的方法包括以下步骤。 提供了至少形成有栅极结构的衬底，并且在栅极结构的顶部上形成至少一个氮化硅硬掩模。 执行第一次去除以用第一磷酸（H 3 PO 4）溶液去除一部分氮化硅硬掩模。 随后进行第二次去除以用第二种磷酸溶液去除残留的氮化硅硬掩模。 第一次去除和第二次去除是原位进行的。 第二磷酸溶液的温度低于第一磷酸溶液的温度。

公开(公告)号：US20150079777A1

公开(公告)日：2015-03-19

申请号：US14029824

申请日：2013-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28

CPC classification number: H01L21/28176 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。

公开(公告)号：US20130256701A1

公开(公告)日：2013-10-03

申请号：US13905148

申请日：2013-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。