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    METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE
    1.
    发明申请
    METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE 审中-公开
    制造多栅极晶体管器件的方法

    公开(公告)号：US20140199817A1

    公开(公告)日：2014-07-17

    申请号：US14219010

    申请日：2014-03-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

    IPC: H01L29/66

    CPC classification number: H01L29/66795

    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

    Abstract translation: 一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层 图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分 覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

    SEMICONDUCTOR STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20140077229A1

    公开(公告)日：2014-03-20

    申请号：US14089771

    申请日：2013-11-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

    IPC: H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

    Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

    Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

    METHOD FOR FORMING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20160190287A1

    公开(公告)日：2016-06-30

    申请号：US14607085

    申请日：2015-01-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

    IPC: H01L29/66 ,  H01L21/306 ,  H01L21/3105

    CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/78

    Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

    Abstract translation: 形成半导体器件的方法包括以下步骤。 首先，提供具有晶体管的衬底，其中晶体管包括源极/漏极区域。 在基板上形成电介质层，并且在电介质层中形成接触插塞以电连接源极/漏极区域。 接下来，在电介质层上形成掩模层，其中掩模层包括第一层和堆叠在其上的第二层。 之后，在掩模层的第二层上形成槽切割图案，并且在掩模层的第一层上形成接触槽图案。 最后，通过使用第一层上的接触槽图案，去除第二层并形成接触开口。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20140295660A1

    公开(公告)日：2014-10-02

    申请号：US14302047

    申请日：2014-06-11

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28

    CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

    Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

    Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 第二界面层和第一高k层至少在沟槽的表面上保形发泡。 复合金属层形成为至少填充沟槽。

    Manufacturing method for semiconductor device having metal gate
    7.
    发明授权
    Manufacturing method for semiconductor device having metal gate 有权
    具有金属栅极的半导体器件的制造方法

    公开(公告)号：US09024393B2

    公开(公告)日：2015-05-05

    申请号：US14140546

    申请日：2013-12-26

    Applicant: United Microelectronics Corp.

    Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

    IPC: H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

    Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

    Manufacturing Method of Non-Planar FET
    8.
    发明申请
    Manufacturing Method of Non-Planar FET 有权
    非平面FET的制造方法

    公开(公告)号：US20150004766A1

    公开(公告)日：2015-01-01

    申请号：US14487103

    申请日：2014-09-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

    IPC: H01L29/66 ,  H01L29/51

    CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

    Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

    MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE
    10.
    发明申请
    MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
    具有金属栅的半导体器件的制造方法

    公开(公告)号：US20140106557A1

    公开(公告)日：2014-04-17

    申请号：US14140546

    申请日：2013-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

    IPC: H01L21/28 ,  H01L21/8238

    CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

    Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

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