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公开(公告)号：US20170285718A1
公开(公告)日：2017-10-05
申请号：US15193125
申请日：2016-06-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen
CPC classification number: G06F1/324 , G06F1/3237 , G06F1/3296 , G06F12/0238 , G06F13/14 , G06F2212/222 , G06F2212/251 , Y02D10/128 , Y02D50/20
Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.
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公开(公告)号：US11334429B2
公开(公告)日：2022-05-17
申请号：US16985241
申请日：2020-08-05
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen , Ying-Che Chung
Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.
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公开(公告)号：US20190073262A1
公开(公告)日：2019-03-07
申请号：US15808808
申请日：2017-11-09
Applicant: VIA Technologies, Inc.
Inventor： Ching-Yu Chen , Yi-Lin Lai , Chen-Te Chen
CPC classification number: G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3715 , H03M13/373
Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.
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公开(公告)号：US10223017B2
公开(公告)日：2019-03-05
申请号：US15193126
申请日：2016-06-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen
IPC: G06F1/32 , G06F3/06 , G06F1/3225 , G06F1/3228 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F1/3206
Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.
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Patent Agency Ranking
公开(公告)号：US20170285989A1
公开(公告)日：2017-10-05
申请号：US15193126
申请日：2016-06-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen
CPC classification number: G06F3/0625 , G06F1/3206 , G06F1/3225 , G06F1/3228 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F3/0634 , G06F3/0679 , G06F3/0688 , Y02D10/14 , Y02D10/152 , Y02D10/154 , Y02D10/171 , Y02D50/20
Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.
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公开(公告)号：US10783032B2
公开(公告)日：2020-09-22
申请号：US15662254
申请日：2017-07-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen , Ying-Che Chung
Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
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公开(公告)号：US10216250B2
公开(公告)日：2019-02-26
申请号：US15193125
申请日：2016-06-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen
IPC: G06F1/32 , G06F12/02 , G06F13/14 , G06F1/324 , G06F1/3237 , G06F1/3296
Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.
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公开(公告)号：US10474529B2
公开(公告)日：2019-11-12
申请号：US15808808
申请日：2017-11-09
Applicant: VIA Technologies, Inc.
Inventor： Ching-Yu Chen , Yi-Lin Lai , Chen-Te Chen
Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.
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公开(公告)号：US20180329776A1
公开(公告)日：2018-11-15
申请号：US15662254
申请日：2017-07-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen , Ying-Che Chung
CPC classification number: G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/152 , H03M13/2906
Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
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