公开(公告)号：US20210229281A1

公开(公告)日：2021-07-29

申请号：US17213741

申请日：2021-03-26

申请人： Venkat Natarajan ,  Arjun Kg ,  Gagan Acharya ,  Amit Sudhir Baxi ,  Rita H. Wouhaybi ,  Wen-Ling Margaret Huang

发明人： Venkat Natarajan ,  Arjun Kg ,  Gagan Acharya ,  Amit Sudhir Baxi ,  Rita H. Wouhaybi ,  Wen-Ling Margaret Huang

IPC分类号： B25J9/16 ,  G05B13/02

摘要： Various aspects of methods, systems, and use cases include techniques for training or using a model to control a robot. A method may include identifying a set of action primitives applicable to a set of robots, receiving information corresponding to a task (e.g., a collaborative task), and determining at least one action primitive based on the received information. The method may include training a model to control operations of at least one robot of the set of robots using the received information and the at least one action primitive.

公开(公告)号：US5670389A

公开(公告)日：1997-09-23

申请号：US585137

申请日：1996-01-11

申请人： Wen-Ling Margaret Huang ,  Hyungcheol Shin ,  Marco Racanelli

发明人： Wen-Ling Margaret Huang ,  Hyungcheol Shin ,  Marco Racanelli

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/265 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78621

摘要： A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.

摘要翻译： 具有横向梯度沟道区（23A，24A）的绝缘体上半导体器件（40）以及制造绝缘体上硅半导体器件（40）的方法。 绝缘体上硅半导体器件（40）具有在半导体层（12）上具有侧壁（19,21）的栅极结构（16）。 轻掺杂区域（26A，27A）在侧壁（19,21）下延伸穿过半导体层（12）的一部分的整个厚度。 在栅极结构（16）的下方形成横向梯度的沟道区（23A），并邻接一个（26A）的轻掺杂区。 源极（33）形成在轻掺杂区域的第一（26A）中，并且在第二（27A）轻掺杂区域中形成漏极区域（34）。

公开(公告)号：US5780352A

公开(公告)日：1998-07-14

申请号：US553801

申请日：1995-10-23

申请人： Heemyong Park ,  Wen-Ling Margaret Huang ,  Juergen Foerstner ,  Marco Racanelli

发明人： Heemyong Park ,  Wen-Ling Margaret Huang ,  Juergen Foerstner ,  Marco Racanelli

IPC分类号： H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/76264 ,  H01L21/32 ,  H01L21/76281

摘要： A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

摘要翻译： 在绝缘体上硅（SOI）衬底（21）上形成隔离氧化物（30）的方法包括在SOI衬底（21）的硅层（24）的区域上设置掩模层（26,27） ）。 隔离氧化物（30）生长在硅层（24）的不同区域（28）中。 隔离氧化物（30）生长到硅层（24）内的深度（32）小于或等于硅层（24）的厚度（29）。 在去除掩模层（26,27）之后，隔离氧化物（30）进一步生长在硅层（24）的不同区域（28）中，使得隔离氧化物（30）与掩埋电绝缘层 （23）内。 埋入的电绝缘层（23）和隔离氧化物（30）电绝缘半导体器件（20）的有源区（43）。