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公开(公告)号:US08697506B2
公开(公告)日:2014-04-15
申请号:US13418566
申请日:2012-03-13
申请人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号: H01L21/335
CPC分类号: H01L29/7787 , H01L29/2003 , H01L29/207
摘要: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
摘要翻译: 提供了一种制造异质结构器件的方法,其包括将离子注入到多层结构的表面的一部分中。 碘离子注入第一区域和第二区域之间以形成第三区域。 电荷从第三区域中的二维电子气(2DEG)通道中消耗,以形成从第一区域到第二区域的可逆的非导电通路。 在向靠近第三区域的栅电极施加电压电位时,允许电流从第一区域流到第二区域。
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公开(公告)号:US08159002B2
公开(公告)日:2012-04-17
申请号:US11961532
申请日:2007-12-20
申请人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号: H01L29/66
CPC分类号: H01L29/7787 , H01L29/2003 , H01L29/207
摘要: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
摘要翻译: 异质结构器件包括具有第一区域,第二区域和第三区域的半导体多层结构。 第一区域耦合到源电极,第二区域耦合到漏电极。 第三区域设置在第一区域和第二区域之间。 第三区域提供从源电极到漏电极的可切换导电路径。 第三区域包括碘离子。 一种系统包括包括该器件的异质结构场效应晶体管。
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公开(公告)号:US20090159929A1
公开(公告)日:2009-06-25
申请号:US11961532
申请日:2007-12-20
申请人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号: H01L29/78 , H01L21/335
CPC分类号: H01L29/7787 , H01L29/2003 , H01L29/207
摘要: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
摘要翻译: 异质结构器件包括具有第一区域,第二区域和第三区域的半导体多层结构。 第一区域耦合到源电极,第二区域耦合到漏电极。 第三区域设置在第一区域和第二区域之间。 第三区域提供从源电极到漏电极的可切换导电路径。 第三区域包括碘离子。 一种系统包括包括该器件的异质结构场效应晶体管。
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公开(公告)号:US20120171824A1
公开(公告)日:2012-07-05
申请号:US13418566
申请日:2012-03-13
申请人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人: Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号: H01L21/335
CPC分类号: H01L29/7787 , H01L29/2003 , H01L29/207
摘要: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
摘要翻译: 提供了一种制造异质结构器件的方法,其包括将离子注入到多层结构的表面的一部分中。 碘离子注入第一区域和第二区域之间以形成第三区域。 电荷从第三区域中的二维电子气(2DEG)通道中消耗,以形成从第一区域到第二区域的可逆的非导电通路。 在向靠近第三区域的栅电极施加电压电位时,允许电流从第一区域流到第二区域。
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公开(公告)号:US20090140293A1
公开(公告)日:2009-06-04
申请号:US11946959
申请日:2007-11-29
申请人: Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Vinayak Tilak , Siddharth Rajan , Ho-Young Cha
发明人: Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Vinayak Tilak , Siddharth Rajan , Ho-Young Cha
IPC分类号: H01L29/778
CPC分类号: H01L29/7786 , H01L29/2003
摘要: A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article.
摘要翻译: 异质结构器件或制品包括载流子传输层,背沟道层和阻挡层。 载流子传输层具有与第一表面相对的第一表面和第二表面。 背沟道层被固定到载流子传输层的第一表面,并且阻挡层固定到载流子传输层的第二表面。 载流子传输层,背沟道层和阻挡层中的每一个包括氮化镓铝合金。 该制品还包括在载流子传输层的第二表面和势垒层的表面的界面处的2D电子气体。 2D电子气体由界面处的带隙差分限定,这允许电子迁移率。 一种系统包括包括该物品的异质结构场效应晶体管。
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公开(公告)号:US07906427B2
公开(公告)日:2011-03-15
申请号:US12251341
申请日:2008-10-14
IPC分类号: H01L21/4763
CPC分类号: H01L29/66068 , H01L22/12 , H01L22/26 , H01L29/0873 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/7813 , Y02P80/30
摘要: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.
摘要翻译: 提供了一种用于半导体器件的尺寸分布的方法。 该方法包括将包括可检测元件的特征结合到该装置中,并且此后检测可检测元件以确定特征的尺寸。 该信息可用于确定掩埋通道的尺寸,也可用于CMP工艺的端点检测。
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公开(公告)号:US20100093116A1
公开(公告)日:2010-04-15
申请号:US12251341
申请日:2008-10-14
IPC分类号: H01L21/66
CPC分类号: H01L29/66068 , H01L22/12 , H01L22/26 , H01L29/0873 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/7813 , Y02P80/30
摘要: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.
摘要翻译: 提供了一种用于半导体器件的尺寸分布的方法。 该方法包括将包括可检测元件的特征结合到该装置中,并且此后检测可检测元件以确定特征的尺寸。 该信息可用于确定掩埋通道的尺寸,也可用于CMP工艺的端点检测。
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公开(公告)号:US20080146004A1
公开(公告)日:2008-06-19
申请号:US11610199
申请日:2006-12-13
CPC分类号: H01L21/0465 , H01L29/66068
摘要: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.
摘要翻译: 公开了一种制造SiC MOSFET的方法。 该方法包括在衬底上生长SiC外延层,平面化SiC外延层以提供平坦化的SiC外延层,以及形成与平坦化的外延层接触的栅极电介质层。
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公开(公告)号:US07589360B2
公开(公告)日:2009-09-15
申请号:US11594473
申请日:2006-11-08
申请人: Kevin Sean Matocha , Vinayak Tilak
发明人: Kevin Sean Matocha , Vinayak Tilak
IPC分类号: H01L29/06
CPC分类号: H01L29/045 , H01L29/2003 , H01L29/94
摘要: A device having an electrode-insulator layer-group III nitride layer structure, wherein an interface between the insulator layer and the group III nitride semiconductor layer lies along a non-polar plane of the group III nitride semiconductor layer is provided.
摘要翻译: 提供了具有电极 - 绝缘体层III族氮化物层结构的器件,其中绝缘体层和III族氮化物半导体层之间的界面位于III族氮化物半导体层的非极性平面。
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公开(公告)号:US20080121927A1
公开(公告)日:2008-05-29
申请号:US11594473
申请日:2006-11-08
申请人: Kevin Sean Matocha , Vinayak Tilak
发明人: Kevin Sean Matocha , Vinayak Tilak
IPC分类号: H01L29/20 , H01L21/336
CPC分类号: H01L29/045 , H01L29/2003 , H01L29/94
摘要: A device having an electrode-insulator layer-group III nitride layer structure, wherein an interface between the insulator layer and the group III nitride semiconductor layer lies along a non-polar plane of the group III nitride semiconductor layer is provided.
摘要翻译: 提供了具有电极 - 绝缘体层III族氮化物层结构的器件,其中绝缘体层和III族氮化物半导体层之间的界面位于III族氮化物半导体层的非极性平面。
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