公开(公告)号：US20070202304A1

公开(公告)日：2007-08-30

申请号：US11362261

申请日：2006-02-27

申请人： Vladimir Golovko ,  Brian Johnson ,  John Robertson ,  Mirco Cantoro ,  Angel Berenguer ,  Wilhelm Huck ,  Hongwei Li ,  Zongqiang Yang

发明人： Vladimir Golovko ,  Brian Johnson ,  John Robertson ,  Mirco Cantoro ,  Angel Berenguer ,  Wilhelm Huck ,  Hongwei Li ,  Zongqiang Yang

IPC分类号： B44C1/17

CPC分类号： B22F1/0022 ,  B01J13/0043 ,  B82Y30/00 ,  Y10T428/24802

摘要： A method for producing a colloid of metallic nanoparticles including the steps of: providing metal ions in solution; providing a stabilizing agent; and reducing said metal ions in the presence of said stabilizing agent, so that metallic nanoparticles are formed with a surrounding layer of said stabilizing agent, wherein the reduction step is carried out at a temperature of not less than 20° C. and not more than 150° C. The metallic nanoparticles are formed of a mixture of transition metal and noble metal, such as Ni—Pd. The resultant nanoparticles have a high stability in terms of size and chemical degradation and so can be stored for long periods. They are therefore particularly suited for forming patterned nanoparticle arrays on a substrate by nanocontact printing for the subsequent formation of a corresponding array of carbon nanotubes or nanofibers via plasma enhanced CVD.

摘要翻译： 一种制造金属纳米粒子胶体的方法，包括以下步骤：在溶液中提供金属离子; 提供稳定剂; 并在所述稳定剂存在下还原所述金属离子，使金属纳米颗粒与所述稳定剂的周围层形成，其中所述还原步骤在不低于20℃且不大于 150℃。金属纳米颗粒由过渡金属和贵金属的混合物如Ni-Pd形成。 所得纳米颗粒在尺寸和化学降解方面具有高稳定性，因此可以长期储存。 因此，它们特别适用于通过纳米接触印刷在衬底上形成图案化纳米颗粒阵列，以便随后通过等离子体增强CVD形成相应阵列的碳纳米管或纳米纤维。

公开(公告)号：US20170352761A1

公开(公告)日：2017-12-07

申请号：US15602593

申请日：2017-05-23

申请人： Mirco Cantoro ,  Yeoncheol Heo

发明人： Mirco Cantoro ,  Yeoncheol Heo

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088

CPC分类号： H01L29/7849 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

摘要： The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

公开(公告)号：US09318491B2

公开(公告)日：2016-04-19

申请号：US14547190

申请日：2014-11-19

申请人： Mirco Cantoro ,  Taeyong Kwon ,  Sangsu Kim ,  Jae-Hwan Lee

发明人： Mirco Cantoro ,  Taeyong Kwon ,  Sangsu Kim ,  Jae-Hwan Lee

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/092 ,  H01L27/088 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/20 ,  H01L29/36

摘要： A semiconductor device includes a substrate, an insulating layer disposed on the substrate and having a trench exposing a surface portion of the substrate, and a channel-forming structure comprising crystalline semiconductor material. The channel-forming structure has a lower portion located in the trench and fins extending upright on the lower portion, where the fins are spaced from each other and are each narrower than an opening of the trench, and the lower portion of the channel forming structure has a higher crystal defect density than the fins of the channel forming structure.

摘要翻译： 半导体器件包括衬底，设置在衬底上并具有暴露衬底的表面部分的沟槽的绝缘层以及包含晶体半导体材料的沟道形成结构。 通道形成结构具有位于沟槽中的下部，并且在下部直立延伸的翅片，其中翅片彼此间隔开并且比沟槽的开口窄，并且通道形成结构的下部 具有比通道形成结构的翅片更高的晶体缺陷密度。

公开(公告)号：US20160141373A1

公开(公告)日：2016-05-19

申请号：US14823229

申请日：2015-08-11

申请人： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

发明人： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC分类号： H01L29/267 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092

CPC分类号： H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

摘要： A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

摘要翻译： 半导体器件包括设置在衬底上的有源图案和与有源图案交叉的栅电极。 有源图案包括衬底上的第一缓冲器图案，第一缓冲器图案上的沟道图案，第一缓冲器图案和沟道图案之间的掺杂图案，以及掺杂图案和沟道图案之间的第二缓冲图案。 掺杂图案包括注入杂质的石墨烯。

公开(公告)号：US09966375B2

公开(公告)日：2018-05-08

申请号：US15049648

申请日：2016-02-22

申请人： Yong-Joon Choi ,  Tae-Yong Kwon ,  Mirco Cantoro ,  Chang-Jae Yang ,  Dong-Hoon Khang ,  Woo-Ram Kim ,  Cheol Kim ,  Seung-Jin Mun ,  Seung-Mo Ha ,  Do-Hyoung Kim ,  Seong-Ju Kim ,  So-Ra You ,  Woong-ki Hong

发明人： Yong-Joon Choi ,  Tae-Yong Kwon ,  Mirco Cantoro ,  Chang-Jae Yang ,  Dong-Hoon Khang ,  Woo-Ram Kim ,  Cheol Kim ,  Seung-Jin Mun ,  Seung-Mo Ha ,  Do-Hyoung Kim ,  Seong-Ju Kim ,  So-Ra You ,  Woong-ki Hong

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/11 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.

公开(公告)号：US10181526B2

公开(公告)日：2019-01-15

申请号：US15602593

申请日：2017-05-23

申请人： Mirco Cantoro ,  Yeoncheol Heo

发明人： Mirco Cantoro ,  Yeoncheol Heo

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66

摘要： The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.