公开(公告)号：US3872494A

公开(公告)日：1975-03-18

申请号：US44093474

申请日：1974-02-08

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： DAVIS JR JOHN R ,  KRISHNA SURINDER

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L29/732 ,  H01L11/06

CPC分类号： H01L29/7325 ,  H01L21/00 ,  H01L29/00

摘要： A high voltage transistor with high speed capability is disposed in a semiconductor body having a thickness greater than about 100 microns. The collector region adjoining one major surface of the semiconductor body has two collector portions: A first collector portion adjoins selected internal portions of the major surface and has an impurity concentration at the major surface of greater than about 8 X 1018 atoms/cm3. A second collector portion adjoins the major surface at peripheral portions contiguously around the first collector portion and adjoins the first collector portion interior of the body at said internal portions and has a resistivity throughout of greater than 30 ohm-cm. Said second collector portion at said internal portions has a substantially uniform thickness of at least about 30 microns and a reach-through voltage less than the avalanche breakdown voltage thereof, and said second collector portion at said peripheral portions has a thickness at least about 20% greater than the thickness of said second collector portion at said internal portions. Further, the width of the second collector portion at said peripheral portions is greater than 1 and preferably less than 3 times the thickness of the second collector portion at said internal portions. The base region of the transistor adjoins the second collector portion interior of the body and has a minority carrier diffusion length at least an order of magnitude greater than the thickness of the base region at said internal portions. Preferably, the first collector portion laterally circumscribes the emitter region of the transistor by at least the thickness of the second collector portion at the internal portions of the body.

摘要翻译： 具有高速能力的高压晶体管设置在厚度大于约100微米的半导体本体中。 与半导体本体的一个主表面相邻的集电极区域具有两个集电部分：第一集电极部分与主表面的选定内部部分相邻，并且在主表面上的杂质浓度大于约8×1018原子/ cm3。 第二收集器部分围绕第一收集器部分连续地邻近周边部分处的主表面，并且在所述内部部分处与主体的第一收集器部分内部相邻并且具有大于30欧姆 - 厘米的电阻率。 在所述内部部分处的所述第二收集器部分具有至少约30微米的基本均匀的厚度和小于其雪崩击穿电压的达到通电电压，并且所述外围部分处的所述第二收集器部分具有至少约20％的厚度， 大于所述第二收集器部分在所述内部部分的厚度。 此外，所述周边部分处的第二集电部分的宽度大于1，优选小于所述内部部分处的第二集电部分的厚度的3倍。 晶体管的基极区域与主体的第二集电极部分内部相邻，并且具有比所述内部部分的基极区域的厚度大至少一个数量级的少量载流子扩散长度。 优选地，第一集电器部分侧向地围绕晶体管的发射极区域至少在主体的内部部分处的第二集电器部分的厚度。

公开(公告)号：US3903542A

公开(公告)日：1975-09-02

申请号：US45027774

申请日：1974-03-11

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： NATHANSON HARVEY C ,  GREEN DAVID ,  DAVIS JR JOHN R

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L27/00 ,  H01L27/07 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/70 ,  H01L29/73 ,  H01L29/74 ,  H01L29/86 ,  H01L29/66

CPC分类号： H01L29/705 ,  H01L27/00 ,  H01L27/0705 ,  H01L29/00 ,  H01L29/0603 ,  H01L29/0684 ,  H01L29/40

摘要： A surface gate-induced semiconductor device is provided which exhibits conductivity modulated transient negative resistance. First and second base electrodes are spaced from each other and make ohmic contact to a semiconductor body adjacent a major surface thereof. An insulator layer with a gate electrode thereon is positioned on a major surface of the semiconductor body between the base electrodes. A gate bias voltage is applied to the gate electrode to form an inversion layer in the semiconductor body at the major surface adjacent the gate electrode. The modulation control signal is also applied to the gate electrode to inject minority carriers from the inversion layer into the semiconductor body and conductivity modulate an electric field applied across the body between the base electrodes by an interbase voltage source. The device is characterized by an operational parameter h 1 greater than 1 and preferably greater than 3. The semiconductor devices can be utilized in a spaced parallel array, preferably with common base electrodes, to form a neuristor device capable of propagating a minority carrier traveling wave without attenuation.

摘要翻译： 提供表面栅感应半导体器件，其表现出导电性调制的瞬态负电阻。 第一和第二基极彼此间隔开并与其主表面相邻的半导体本体欧姆接触。 其上具有栅电极的绝缘体层位于基极之间的半导体本体的主表面上。 栅极偏置电压施加到栅电极，在与栅电极相邻的主表面处在半导体本体中形成反型层。 调制控制信号也被施加到栅电极，以将少数载流子从反型层注入到半导体本体中，并通过基极间电压源对基极之间的电场进行导电调制。 该器件的特征在于大于1且优选大于3的操作参数h 1。半导体器件可以以间隔开的平行阵列（优选与公共基极）一起使用，以形成能够传播少数的神经元器件 载波行波无衰减。