公开(公告)号：US08592917B2

公开(公告)日：2013-11-26

申请号：US13235302

申请日：2011-09-16

申请人： Syotaro Ono ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita ,  Toshiyuki Naka

发明人： Syotaro Ono ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita ,  Toshiyuki Naka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238

摘要： According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

公开(公告)号：US08816410B2

公开(公告)日：2014-08-26

申请号：US13357381

申请日：2012-01-24

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/772

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7395

摘要： A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

摘要翻译： 实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。 第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。 第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。 第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。 第二控制电极的电阻高于第三控制电极的电阻。

公开(公告)号：US08482028B2

公开(公告)日：2013-07-09

申请号：US13424340

申请日：2012-03-19

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/7811 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66712

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，以及周期性阵列结构，其具有第一导电类型的第二半导体层和周期性排列在第一半导体上的第二导电类型的第三半导体层 层在与第一半导体层的主表面平行的方向上。 第二半导体层和第三半导体层以点形式设置在第一半导体层上。 周期性阵列结构的最外围部分中的周期性结构不同于最外周部​​分以外的部分的周期性阵列结构的周期性结构。

公开(公告)号：US20120217555A1

公开(公告)日：2012-08-30

申请号：US13357381

申请日：2012-01-24

申请人： Wataru SAITO ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru SAITO ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/772

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7395

摘要： A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

摘要翻译： 实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。 第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。 第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。 第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。 第二控制电极的电阻高于第三控制电极的电阻。

公开(公告)号：US08643091B2

公开(公告)日：2014-02-04

申请号：US13052028

申请日：2011-03-18

申请人： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device includes first, second, third, and fourth semiconductor layers of alternating first and second conductivity types, an embedded electrode in a first trench that penetrates through the second semiconductor layer, a control electrode above the embedded electrode in the first trench, and first and second main electrodes. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench, which penetrates through the second semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer, and the second main electrode is in the second trench and electrically connected to the second, third, and fourth semiconductor layers. The embedded electrode is electrically connected to the second main electrode or the control electrode. A Shottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.

摘要翻译： 半导体器件包括交替的第一和第二导电类型的第一，第二，第三和第四半导体层，穿透第二半导体层的第一沟槽中的嵌入电极，在第一沟槽中的嵌入电极上方的控制电极，以及 第一和第二主电极。 第四半导体层选择性地设置在第一半导体层中，并且连接到穿过第二半导体层的第二沟槽的下端。 第一主电极与第一半导体层电连接，第二主电极位于第二沟槽中，并与第二，第三和第四半导体层电连接。 嵌入电极与第二主电极或控制电极电连接。 在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。

公开(公告)号：US09048313B2

公开(公告)日：2015-06-02

申请号：US13607697

申请日：2012-09-08

申请人： Syotaro Ono ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Syotaro Ono ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/7827 ,  H01L21/02697 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

摘要翻译： 半导体器件包括半导体衬底和多个栅电极，其包括在与半导体衬底平行的平面中沿第一方向延伸的部分。 所述半导体衬底具有包括多个第一导电型柱和第二导电型第二柱的第二半导体层，所述第二导电型柱和第二导电型第二柱设置在所述第一半导体层上，在与所述半导体衬底平行的平面中沿所述第一方向延伸，并且在第三方向上相交 具有与第一方向正交的第二方向，并且以交替的方式彼此相邻布置。

公开(公告)号：US09093474B2

公开(公告)日：2015-07-28

申请号：US13600616

申请日：2012-08-31

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

摘要翻译： 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

公开(公告)号：US20130248988A1

公开(公告)日：2013-09-26

申请号：US13607697

申请日：2012-09-08

申请人： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/7827 ,  H01L21/02697 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

摘要翻译： 半导体器件包括半导体衬底和多个栅电极，其包括在与半导体衬底平行的平面中沿第一方向延伸的部分。 所述半导体衬底具有包括多个第一导电型柱和第二导电型第二柱的第二半导体层，所述第二导电型柱和第二导电型第二柱设置在所述第一半导体层上，在与所述半导体衬底平行的平面中沿所述第一方向延伸，并且在第三方向上相交 具有与第一方向正交的第二方向，并且以交替的方式彼此相邻布置。

公开(公告)号：US20130221426A1

公开(公告)日：2013-08-29

申请号：US13600616

申请日：2012-08-31

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

摘要翻译： 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

公开(公告)号：US20120012929A1

公开(公告)日：2012-01-19

申请号：US13051987

申请日：2011-03-18

申请人： Wataru SAITO ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru SAITO ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/66734

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第一导电类型的第二半导体层，第二导电类型的第三半导体层，第二导电类型的第四半导体层， 第一导电类型的第五半导体层，第一导电类型的控制电极，第一主电极，第二主电极和第六半导体层。 第二半导体层和第三半导体层在与第一半导体层的主表面大致平行的方向上交替地设置在第一半导体层上。 第四半导体层设置在第二半导体层和第三半导体层上。 第五半导体层选择性地设置在第四半导体层的表面上。 控制电极通过绝缘膜设置在沟槽中。 沟槽从第五半导体层的表面穿过第四半导体层并且与第二半导体层接触。 第一主电极连接到第一半导体层。 第二主电极连接到第四半导体层和第五半导体层。 第六半导体层设置在第四半导体层和第二半导体层之间。 第六半导体层的杂质浓度高于第二半导体层的杂质浓度。