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公开(公告)号：US06344383B1
公开(公告)日：2002-02-05
申请号：US09421853
申请日：1999-10-20
IPC分类号： H01L218238
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
摘要翻译： 本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接 其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成 相应较薄的中心区域。
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公开(公告)号：US06674134B2
公开(公告)日：2004-01-06
申请号：US09173430
申请日：1998-10-15
IPC分类号： H01L2976
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
摘要翻译： 本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接 其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成 相应较薄的中心区域。
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公开(公告)号：US08184465B2
公开(公告)日：2012-05-22
申请号：US12911379
申请日：2010-10-25
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US07872897B2
公开(公告)日：2011-01-18
申请号：US10552971
申请日：2003-04-30
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US08724365B2
公开(公告)日：2014-05-13
申请号：US13427162
申请日：2012-03-22
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US20120178239A1
公开(公告)日：2012-07-12
申请号：US13427162
申请日：2012-03-22
IPC分类号： H01L21/768
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US20110032025A1
公开(公告)日：2011-02-10
申请号：US12911379
申请日：2010-10-25
IPC分类号： H01H37/76 , H01L21/768
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US5858866A
公开(公告)日：1999-01-12
申请号：US753234
申请日：1996-11-22
申请人： Wayne S. Berry , Juergen Faul , Wilfried Haensch , Rick L. Mohler
发明人： Wayne S. Berry , Juergen Faul , Wilfried Haensch , Rick L. Mohler
IPC分类号： H01L29/78 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L21/3205 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/28123 , H01L21/823456 , Y10S977/888 , Y10S977/938
摘要： Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel. Thus the conduction characteristic near cut-off can be tailored to specific applications and conduction/cut-off threshold voltage can be reduced at will utilizing a simple, efficient and high-yield manufacturing process.
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公开(公告)号：US6022796A
公开(公告)日：2000-02-08
申请号：US120190
申请日：1998-07-22
申请人： Wayne S. Berry , Juergen Faul , Wilfried Haensch , Rick L. Mohler
发明人： Wayne S. Berry , Juergen Faul , Wilfried Haensch , Rick L. Mohler
IPC分类号： H01L29/78 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L21/3205 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/28123 , H01L21/823456 , Y10S977/888 , Y10S977/938
摘要： Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel. Thus the conduction characteristic near cut-off can be tailored to specific applications and conduction/cut-off threshold voltage can be reduced at will utilizing a simple, efficient and high-yield manufacturing process.
摘要翻译： 场效应晶体管的导通通道中的角导通由导电沟道侧面的栅极氧化物和栅电极的几何结构来控制。 在沟槽结构的边缘（例如深沟槽或浅沟槽隔离结构）和/或沟槽电容器的边缘处四舍五入，在有源区和沟槽结构的界面处在衬底的表面中形成凹槽，其中一部分 形成栅极氧化物和栅电极，使得栅极氧化物和栅电极有效地围绕晶体管的导电沟道的一部分。 特别是当根据亚微米设计规则形成这种晶体管时，栅电极的几何形状允许在没有角度注入的情况下改变传导通道中的电场，以调节传导通道中拐角传导的影响。 因此，接近截止点的导电特性可以根据具体应用进行调整，并且可以利用简单，有效和高产量的制造工艺来降低导通/截止阈值电压。
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公开(公告)号：US5466626A
公开(公告)日：1995-11-14
申请号：US168703
申请日：1993-12-16
申请人： Michael Armacost , A. Richard Baker, Jr. , Wayne S. Berry , Daniel A. Carl , Donald M. Kenney , Thomas J. Licata
发明人： Michael Armacost , A. Richard Baker, Jr. , Wayne S. Berry , Daniel A. Carl , Donald M. Kenney , Thomas J. Licata
IPC分类号： H01L21/02 , H01L21/033 , H01L21/8242
CPC分类号： H01L28/92 , B82Y10/00 , H01L21/0332 , H01L21/0338 , H01L27/1085 , H01L27/10852 , H01L28/84 , Y10S148/105 , Y10S438/947 , Y10S438/964 , Y10S977/81 , Y10S977/888
摘要： The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.
摘要翻译： 本发明提供一种在诸如电容器的衬底中形成凹槽的方法，以增加其表面积，从而增加电容器的电荷存储容量。 这是通过利用在基板的表面上通过附聚形成的微掩模来实现的。 将聚集的材料，例如金，氮化钛或硅化钛用作掩模，用于选择性地蚀刻基板以在其中形成凹部。 或者，氧化物转移掩模可以与聚集的材料微掩模一起使用以蚀刻基底。
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