公开(公告)号：US08987813B2

公开(公告)日：2015-03-24

申请号：US13571366

申请日：2012-08-10

申请人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/7825

摘要： A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.

摘要翻译： 高压金属氧化物半导体晶体管器件包括至少形成在衬底中的隔离结构的衬底，形成在衬底上的栅极，以及形成在栅极各侧的衬底中的源极区和漏极区。 隔离结构还包括凹部。 栅极包括形成在基板的表面上的第一栅极部分和从第一栅极部分向下延伸并形成在凹部中的第二栅极部分。

公开(公告)号：US08852990B2

公开(公告)日：2014-10-07

申请号：US13589179

申请日：2012-08-20

申请人： Wei-Lin Chen ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Ke-Feng Lin

发明人： Wei-Lin Chen ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Ke-Feng Lin

IPC分类号： H01L31/18 ,  H01L31/0224 ,  H01L31/0236

CPC分类号： H01L31/18 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.

摘要翻译： 制造太阳能电池的方法包括以下步骤。 首先，提供包括掺杂层的衬底。 随后，在衬底上形成部分地与掺杂层重叠的图案化材料层，并且第一金属层保形地形成在图案化材料层和掺杂层上。 此外，在第一金属层上形成与图案化材料层完全重叠的图案化掩模层，并且在不与图案化材料层重叠的掺杂层上形成第二金属层。 然后，去除图案化掩模层，图案化掩模层和图案化材料层之间的第一金属层和图案化材料层的一部分。

公开(公告)号：US20140051202A1

公开(公告)日：2014-02-20

申请号：US13589179

申请日：2012-08-20

申请人： Wei-Lin Chen ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Ke-Feng Lin

发明人： Wei-Lin Chen ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Ke-Feng Lin

IPC分类号： H01L31/18

CPC分类号： H01L31/18 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.

摘要翻译： 制造太阳能电池的方法包括以下步骤。 首先，提供包括掺杂层的衬底。 随后，在衬底上形成部分地与掺杂层重叠的图案化材料层，并且第一金属层保形地形成在图案化材料层和掺杂层上。 此外，在第一金属层上形成与图案化材料层完全重叠的图案化掩模层，并且在不与图案化材料层重叠的掺杂层上形成第二金属层。 然后，去除图案化掩模层，图案化掩模层和图案化材料层之间的第一金属层和图案化材料层的一部分。

公开(公告)号：US20140042527A1

公开(公告)日：2014-02-13

申请号：US13571366

申请日：2012-08-10

申请人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Wei-Lin Chen ,  Chih-Chung Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/7825

摘要： A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.

摘要翻译： 高压金属氧化物半导体晶体管器件包括至少形成在衬底中的隔离结构的衬底，形成在衬底上的栅极，以及形成在栅极各侧的衬底中的源极区和漏极区。 隔离结构还包括凹部。 栅极包括形成在基板的表面上的第一栅极部分和从第一栅极部分向下延伸并形成在凹部中的第二栅极部分。

公开(公告)号：US20130277742A1

公开(公告)日：2013-10-24

申请号：US13454149

申请日：2012-04-24

申请人： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/7816

摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.

摘要翻译： 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。

公开(公告)号：US08766358B2

公开(公告)日：2014-07-01

申请号：US13454149

申请日：2012-04-24

申请人： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/76

CPC分类号： H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/7816

摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.

摘要翻译： 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。

公开(公告)号：US09159791B2

公开(公告)日：2015-10-13

申请号：US13489467

申请日：2012-06-06

申请人： Wei-Lin Chen ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Chih-Chung Wang

发明人： Wei-Lin Chen ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Chih-Chung Wang

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L21/225 ,  H01L21/265 ,  H01L29/45

CPC分类号： H01L29/0878 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/7809

摘要： A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的掩埋层; 深井设置在半导体衬底中; 设置在所述深阱中的第一掺杂区，其中所述第一掺杂区接触所述掩埋层; 导电区域，具有围绕并邻近第一掺杂区域的第一导电类型，其中导电区域的浓度高于第一掺杂区域; 设置在所述第一掺杂区域中的第一重掺杂区域; 具有设置在深井中的具有第二导电类型的阱; 设置在井中的第二重掺杂区域; 设置在所述第一重掺杂区域和所述第二重掺杂区域之间的所述半导体衬底上的栅极; 以及第一沟槽结构和第二沟槽结构，其中所述第二沟槽结构的深度比所述掩埋层的深度更深。

公开(公告)号：US20130328123A1

公开(公告)日：2013-12-12

申请号：US13489467

申请日：2012-06-06

申请人： Wei-Lin Chen ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Chih-Chung Wang

发明人： Wei-Lin Chen ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Chih-Chung Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/7809

摘要： A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的掩埋层; 深井设置在半导体衬底中; 设置在所述深阱中的第一掺杂区，其中所述第一掺杂区接触所述掩埋层; 导电区域，具有围绕并邻近第一掺杂区域的第一导电类型，其中导电区域的浓度高于第一掺杂区域; 设置在所述第一掺杂区域中的第一重掺杂区域; 具有设置在深井中的具有第二导电类型的阱; 设置在井中的第二重掺杂区域; 设置在所述第一重掺杂区域和所述第二重掺杂区域之间的所述半导体衬底上的栅极; 以及第一沟槽结构和第二沟槽结构，其中所述第二沟槽结构的深度比所述掩埋层的深度更深。

公开(公告)号：US08698247B2

公开(公告)日：2014-04-15

申请号：US13156352

申请日：2011-06-09

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。

公开(公告)号：US08836067B2

公开(公告)日：2014-09-16

申请号：US13525471

申请日：2012-06-18

申请人： Ming-Shun Hsu ,  Wen-Peng Hsu ,  Ke-Feng Lin ,  Min-Hsuan Tsai ,  Chih-Chung Wang

发明人： Ming-Shun Hsu ,  Wen-Peng Hsu ,  Ke-Feng Lin ,  Min-Hsuan Tsai ,  Chih-Chung Wang

IPC分类号： H01L27/146

CPC分类号： H01L29/0878 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66681 ,  H01L29/7816

摘要： A transistor device and a manufacturing method thereof are provided. The transistor device includes a substrate, a first well, a second well, a shallow trench isolation (STI), a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The STI is disposed in the second well. The STI has at least one floating diffusion island. The source is disposed in the first well. The drain is disposed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. The gate is disposed above the first well and the second well, and partially overlaps the first well and the second well.

摘要翻译： 提供一种晶体管器件及其制造方法。 晶体管器件包括衬底，第一阱，第二阱，浅沟槽隔离（STI），源极，漏极和栅极。 第一个井被设置在基板中。 第二孔设置在基板中。 STI布置在第二个孔中。 STI具有至少一个浮动扩散岛。 源放置在第一个井中。 排水口设置在第二个井中。 浮动扩散岛的电气类型与漏极不同或相同。 门设置在第一井和第二井的上方，并且部分地与第一井和第二井重叠。