Segmented MRAM memory array
    1.
    发明授权
    Segmented MRAM memory array 有权
    分段MRAM存储器阵列

    公开(公告)号:US07203129B2

    公开(公告)日:2007-04-10

    申请号:US10780171

    申请日:2004-02-16

    IPC分类号: G11C8/00

    摘要: In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to each bit line. Each second diode includes an anode, and a cathode coupled to each word line. The magnetic tunnel junction memories include a pinned layer, a free layer, and a non-magnetic layer. The non-magnetic layer is located between the pinned layer and the free layer. Each diode is positioned at crossing points of the bit lines and the word lines and connected between the first diode at the corresponding crossing bit line and the second diode at the corresponding crossing word line.

    摘要翻译: 在一个示例中,MRAM存储器阵列包括多个字线,与字线交叉的多个位线,以及多个第一和第二二极管以及磁性隧道结存储器。 每个第一二极管包括阴极和耦合到每个位线的阳极。 每个第二二极管包括阳极和耦合到每个字线的阴极。 磁性隧道结存储器包括钉扎层,自由层和非磁性层。 非磁性层位于被钉扎层和自由层之间。 每个二极管位于位线和字线的交叉点处,并连接在相应交叉位线处的第一二极管和相应交叉字线处的第二二极管之间。

    MRAM cell with reduced write current
    3.
    发明授权
    MRAM cell with reduced write current 有权
    降低写入电流的MRAM单元

    公开(公告)号:US07170775B2

    公开(公告)日:2007-01-30

    申请号:US11030453

    申请日:2005-01-06

    IPC分类号: G11C11/00

    CPC分类号: G11C11/16 G11C5/063

    摘要: A magnetic random access memory (MRAM) cell that includes an MRAM stack and a conductive line for carrying write current associated with the MRAM cell. The conductive line is oriented in a direction that is angularly offset from an easy axis of the MRAM stack by an acute angle, such as about 45 degrees.

    摘要翻译: 磁性随机存取存储器(MRAM)单元,其包括用于承载与MRAM单元相关联的写入电流的MRAM堆叠和导线。 导线沿着与MRAM堆叠的容易轴成角度偏移的方向定向为锐角,例如约45度。

    System and method for passing high energy particles through a mask
    4.
    发明授权
    System and method for passing high energy particles through a mask 有权
    将高能粒子通过掩模的系统和方法

    公开(公告)号:US07151271B2

    公开(公告)日:2006-12-19

    申请号:US10681541

    申请日:2003-10-08

    IPC分类号: A61N5/00 G21G5/00

    摘要: A method and system is disclosed for concentrating high energy particles on a predetermined area on a target semiconductor substrate. A high energy source for generating a predetermined amount of high energy particles, and an electro-magnetic radiation source for generating low energy beams are used together. The system also uses a mask set having at least one mask with at least one alignment area and at least one mask target area thereon, the mask target area passing more high energy particles then any other area of the mask. At least one protection shield is incorporated in the system for protecting the alignment area from being exposed to the high energy particles, wherein the mask is aligned with the predetermined target semiconductor substrate by passing the low energy beams through the alignment area, wherein the high energy particles generated by the high energy source pass through the mask target area to land on the predetermined area on the target semiconductor substrate.

    摘要翻译: 公开了一种用于将高能粒子集中在目标半导体衬底上的预定区域上的方法和系统。 用于产生预定量的高能粒子的高能量源和用于产生低能量束的电磁辐射源一起使用。 该系统还使用具有至少一个具有至少一个对准区域和至少一个掩模目标区域的掩模的掩模组,掩模目标区域通过更多的高能粒子,然后通过掩模的任何其它区域。 至少一个保护屏蔽被并入系统中,用于保护对准区域不暴露于高能粒子,其中通过使低能量束通过对准区域,掩模与预定目标半导体衬底对齐,其中高能量 由高能量源产生的粒子通过掩模对象区域落在目标半导体衬底上的预定区域上。

    Interdigitated capacitor and method for fabrication therof
    5.
    发明申请
    Interdigitated capacitor and method for fabrication therof 有权
    交叉电容器及其制造方法

    公开(公告)号:US20050206469A1

    公开(公告)日:2005-09-22

    申请号:US10804899

    申请日:2004-03-19

    IPC分类号: H01L23/522 H01P1/36

    摘要: A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.

    摘要翻译: 在微电子产品中使用的电容器采用第一电容器板层,其包括第一系列水平分离和互连的尖齿。 电容器电介质层将第一电容器板层与第二电容器板层分开。 第二电容器板层包括与第一系列水平分离和互相联接的齿水平地交叉指向的第二系列水平分离和互连的齿。 使用自对准方法形成电容器,并且电容器介电层形成为蛇形形状。

    MRAM arrays and methods for writing and reading magnetic memory devices
    6.
    发明授权
    MRAM arrays and methods for writing and reading magnetic memory devices 有权
    MRAM阵列和写入和读取磁存储器件的方法

    公开(公告)号:US07436698B2

    公开(公告)日:2008-10-14

    申请号:US11610739

    申请日:2006-12-14

    IPC分类号: G11C11/00

    CPC分类号: G11C11/1673

    摘要: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.

    摘要翻译: 一种用于写入和读取磁存储单元的非破坏性技术和相关阵列,包括对与选择存储器单元相对应的所选读取行的第一信号进行采样,向选择存储单元施加磁场,对所选择的读取的第二信号 并且比较第一和第二信号以确定选择存储器单元的逻辑状态。

    MRAM arrays and methods for writing and reading magnetic memory devices
    8.
    发明申请
    MRAM arrays and methods for writing and reading magnetic memory devices 有权
    MRAM阵列和写入和读取磁存储器件的方法

    公开(公告)号:US20050243598A1

    公开(公告)日:2005-11-03

    申请号:US11115422

    申请日:2005-04-27

    IPC分类号: G11C11/00 G11C11/16

    CPC分类号: G11C11/1673

    摘要: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.

    摘要翻译: 一种用于写入和读取磁存储单元的非破坏性技术和相关阵列,包括对与选择存储器单元相对应的所选读取行的第一信号进行采样,向选择存储单元施加磁场,对所选择的读取的第二信号 并且比较第一和第二信号以确定选择存储器单元的逻辑状态。

    Segmented MRAM memory array
    9.
    发明申请
    Segmented MRAM memory array 有权
    分段MRAM存储器阵列

    公开(公告)号:US20050180203A1

    公开(公告)日:2005-08-18

    申请号:US10780171

    申请日:2004-02-16

    IPC分类号: G11C11/14 G11C11/16

    摘要: In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to each bit line. Each second diode includes an anode, and a cathode coupled to each word line. The magnetic tunnel junction memories include a pinned layer, a free layer, and a non-magnetic layer. The non-magnetic layer is located between the pinned layer and the free layer. Each diode is positioned at crossing points of the bit lines and the word lines and connected between the first diode at the corresponding crossing bit line and the second diode at the corresponding crossing word line.

    摘要翻译: 在一个示例中,MRAM存储器阵列包括多个字线,与字线交叉的多个位线,以及多个第一和第二二极管以及磁性隧道结存储器。 每个第一二极管包括阴极和耦合到每个位线的阳极。 每个第二二极管包括阳极和耦合到每个字线的阴极。 磁性隧道结存储器包括钉扎层,自由层和非磁性层。 非磁性层位于被钉扎层和自由层之间。 每个二极管位于位线和字线的交叉点处,并连接在相应交叉位线处的第一二极管和相应交叉字线处的第二二极管之间。

    Method for forming a reduced active area in a phase change memory structure
    10.
    发明授权
    Method for forming a reduced active area in a phase change memory structure 有权
    在相变存储器结构中形成减小的有效面积的方法

    公开(公告)号:US08153471B2

    公开(公告)日:2012-04-10

    申请号:US12945860

    申请日:2010-11-14

    IPC分类号: H01L21/06

    摘要: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

    摘要翻译: 一种相变存储器结构及其形成方法,所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物,其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积,从而减少所需的相变电流。