公开(公告)号：US20100147565A1

公开(公告)日：2010-06-17

申请号：US12333746

申请日：2008-12-12

申请人： Wen-Jeng Fan ,  Ching-Wei Hung ,  Tsai-Chuan Yu

发明人： Wen-Jeng Fan ,  Ching-Wei Hung ,  Tsai-Chuan Yu

IPC分类号： H01R12/36

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/4824 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A window ball grid array substrate and its package structure includes a package substrate with a long slot arranged thereon, wherein the improvement is characterized by the long slot penetrating an end of the package substrate making the package substrate appear to be U-shaped.

摘要翻译： 窗户球栅格阵列基板及其封装结构包括其上布置有长槽的封装基板，其特征在于，所述改进的特征在于穿过封装基板的端部的长槽，使封装基板看起来呈U形。

公开(公告)号：US07732921B2

公开(公告)日：2010-06-08

申请号：US12056797

申请日：2008-03-27

申请人： Wen-Jeng Fan ,  Yi-Ling Liu ,  Shin-Hui Huang ,  Tsai-Chuan Yu

发明人： Wen-Jeng Fan ,  Yi-Ling Liu ,  Shin-Hui Huang ,  Tsai-Chuan Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/49 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/242 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections.

摘要翻译： 揭示了一种窗型BGA半导体封装，主要包括具有引线键合槽的衬底，设置在衬底顶表面上的芯片以及穿过引线接合槽的多个接合线。 在基板的底面上形成有多个电镀线短截线，将基板上的接合爪连接到引线接合槽。 接合线将芯片的接合焊盘电连接到衬底的相应接合指状物。 电镀线短截线与在接合指状物处相对应地连接的接合线的引线接合路径（例如平行于重叠布置），以避免电镀线短截线和接合线之间的电短路，没有相应的电气关系 连接。

公开(公告)号：US20080237855A1

公开(公告)日：2008-10-02

申请号：US11727902

申请日：2007-03-28

申请人： Wen-Jeng Fan ,  Tsai-Chuan Yu

发明人： Wen-Jeng Fan ,  Tsai-Chuan Yu

IPC分类号： H01L23/488

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.

摘要翻译： 公开了一种用于封装的BGA封装和衬底。 芯片设置在基板的顶表面上。 多个焊球设置在形成在基板的底表面上的多个球垫上。 衬底至少具有芯层，其具有填充有低模量材料作为应力缓冲器的多个角腔。 此外，基板的角部处的一些球垫设置在角空腔的下方。

公开(公告)号：US08240029B2

公开(公告)日：2012-08-14

申请号：US12274694

申请日：2008-11-20

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01R43/00 ,  H01R43/16

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method for forming an isolated inner lead from a leadframe is revealed. The leadframe primarily comprises a plurality of leads, the isolated inner lead, and an external lead. Each lead has an inner portion having a finger. The isolated inner lead having two fingers is completely formed inside a molding area and is made of the same metal leadframe as the leads. One finger of the isolated inner lead and the fingers of the leads are linearly arranged. The other finger of the isolated inner lead is adjacent to a finger of the external lead. At least one of the inner portions divides the isolated inner lead from the external lead. The isolated inner lead is integrally connected to an adjacent one of the inner portions by a connecting block. A tape-attaching step is performed to mechanically connect the isolated inner lead where two insulating tapes are attached in a manner that the connecting block can be removed. Therefore, the isolated inner lead is electrically isolated from the leads and can be mechanically fixed to replace extra redistributing components during semiconductor packaging processes.

摘要翻译： 揭示了从引线框形成隔离内引线的方法。 引线框架主要包括多个引线，隔离内引线和外引线。 每个引线具有具有手指的内部部分。 具有两个指状物的隔离内部引线在成型区域内完全形成，并且由与引线相同的金属引线框构成。 隔离的内引线和引线的指状物的一个指状物线性排列。 隔离的内引线的另一个手指与外引线的手指相邻。 内部部分中的至少一个将隔离的内部引线与外部引线分开。 隔离的内引线通过连接块一体连接到相邻的一个内部部分。 执行胶带附着步骤以将连接块移除的方式机械地连接隔离的内引线，其中两个绝缘带被附接。 因此，隔离的内部引线与引线电隔离，并且可以机械固定以在半导体封装工艺期间替换额外的再分配组件。

公开(公告)号：US07723828B2

公开(公告)日：2010-05-25

申请号：US12068613

申请日：2008-02-08

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.

摘要翻译： LOC引线框架半导体封装包括具有多排焊盘的芯片。 至少一个母线连接在芯片上，并且设置在第一排接合焊盘和引线的指状物之间。 多个接合线将第一排接合焊盘电连接到引线的指状物。 汇流条附接到芯片的有效表面的部分包括弯曲部分，该弯曲部分远离手指弯曲。 长接合线通过超过弯曲部分将第二排接合焊盘中的一个电线连接到引线的一个指状物。 因此，长接合线和母线之间的距离增加，以避免长接合线和母线之间的电短路并且提高LOC半导体封装的电连接的质量。

公开(公告)号：US07675186B2

公开(公告)日：2010-03-09

申请号：US11514349

申请日：2006-09-01

申请人： Cheng-Ping Chen ,  Wen-Jeng Fan

发明人： Cheng-Ping Chen ,  Wen-Jeng Fan

IPC分类号： H01L23/29

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.

摘要翻译： IC封装主要包括具有槽的衬底，芯片，保护性密封剂，加强密封剂和多个外部端子。 加强密封剂的杨氏模量大于保护性密封剂中的一种，并且硬化密封剂的固化收缩率小于保护性密封剂中的一种。 保护性密封剂形成在用于封装芯片的衬底的一个表面上。 加强密封剂从设置有外部端子的基板的另一个表面突出。 此外，加强密封剂形成在槽内并与芯片接触。 由于加强型密封剂嵌入并形成在槽内，因此，加强密封剂与基板的接触面积增加，以提高IC封装的抗翘曲性。

公开(公告)号：US20090137069A1

公开(公告)日：2009-05-28

申请号：US11987235

申请日：2007-11-28

申请人： Li-Chih Fang ,  Wen-Jeng Fan

发明人： Li-Chih Fang ,  Wen-Jeng Fan

IPC分类号： H01L21/66

CPC分类号： H01L21/78 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

摘要： A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.

摘要翻译： 芯片封装过程集成了老化测试或高温测试，以简化整个封装和测试流程。 一个或多个芯片设置在衬底条的一个或多个单元上，其中衬底带在电镀线处具有多个电开路部分，以在不同单元之间电隔离外部焊盘。 在电连接和封装之后，在后模具固化步骤的同时进行老化测试，如果需要进行高温测试。 因此，在模塑固化步骤期间封装剂完全固化之前，衬底条上的芯片已经经过老化测试，并且在分离步骤之前完成老化测试以减少整体测试时间。

公开(公告)号：US20090039490A1

公开(公告)日：2009-02-12

申请号：US11889018

申请日：2007-08-08

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/12

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09736 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of the semiconductor package, the external terminals are divided into at least two different groups. In one of the embodiment, different groups of the external terminals are bumps with non-equal heights to achieve a uniform standoff plane to compensate the warpage of the substrate. The predicted substrate warpage can be compensated without causing any soldering defects. In another embodiment, a plurality of compensating bumps are selectively disposed on one group of the external terminals with larger stacking gaps.

摘要翻译： 揭示了半导体封装的安装组件，主要包括至少具有多个外部端子的半导体封装，封装载体和焊膏。 焊膏将外部端子连接到封装载体。 根据与半导体封装的基板上的中心线的距离，将外部端子划分为至少两个不同的组。 在一个实施例中，不同组的外部端子是具有不相等高度的凸块，以实现均匀的支座平面以补偿基板的翘曲。 可以补偿预测的基板翘曲而不引起任何焊接缺陷。 在另一个实施例中，多个补偿凸块选择性地设置在具有较大堆积间隙的一组外部端子上。

公开(公告)号：US20080272489A1

公开(公告)日：2008-11-06

申请号：US11824448

申请日：2007-06-29

申请人： Li-Chih Fang ,  Ronald Iwata ,  Wen-Jeng Fan

发明人： Li-Chih Fang ,  Ronald Iwata ,  Wen-Jeng Fan

IPC分类号： H01L23/485

CPC分类号： H05K3/3452 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball.

摘要翻译： 具有焊盘的半导体芯片基板包括芯层和形成在芯层表面上的至少一个导电结构; 绝缘层，其具有覆盖所述导电结构的至少一个图案化开口，其中所述图案化开口具有在所述中心部分的周边边缘上的中心部分和多个翼部，以限定所述导电结构的暴露区域作为所述焊盘。 具有机翼的焊盘将改善焊盘和焊球之间的粘附效应。

公开(公告)号：US20080179720A1

公开(公告)日：2008-07-31

申请号：US11657716

申请日：2007-01-25

申请人： Wen-Jeng Fan ,  Yi-Ling Liu

发明人： Wen-Jeng Fan ,  Yi-Ling Liu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package and a lead frame used in the chip package are disclosed. The lead frame includes a plurality of first side leads and a plurality of second side leads where the first side leads have a plurality of first bent leads extending from a first edge and the second side leads have a plurality of second bent leads extending from a second edge. The inner ends of the first bent leads and the inner ends of the second bent leads are facing to a third edge between the first and second edges and are connected to the lead frame. Therefore, the lengths of the first side leads are equal and symmetrical to the ones of the second side leads without any suspended long leads for chip attachment. The chip package is most suitable for packaging chips with bonding pads on one single side.

摘要翻译： 公开了一种用于芯片封装的芯片封装和引线框架。 引线框架包括多个第一侧引线和多个第二侧引线，其中第一侧引线具有从第一边缘延伸的多个第一弯曲引线，并且第二侧引线具有多个从第二边引出的第二弯曲引线 边缘。 第一弯曲引线的内端和第二弯曲引线的内端面向第一和第二边缘之间的第三边缘并且连接到引线框架。 因此，第一侧引线的长度与第二侧引线的长度相等且对称，而没有用于芯片附接的任何悬挂的长引线。 芯片封装最适合在一个单面封装具有焊盘的芯片。