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公开(公告)号：US11636153B2
公开(公告)日：2023-04-25
申请号：US17332986
申请日：2021-05-27
发明人： Shay Benisty , Ishai Ilani , Tomer Geron
IPC分类号： G06F12/0817 , G06F3/06 , G06F16/901
摘要： Disclosed herein is a computer-implemented method for storing binary tree data in memory. The binary tree data comprises parent node data, first child node data and second child node data. The computer-implemented method comprises determining a first child node memory address, the first child node memory address being less than a parent node memory address; determining a second child node memory address, the second child node memory address being greater than the parent node memory address; storing the parent node data at the parent node memory address; storing the first child node data at the first child node memory address; and storing the second child node data at the second child node memory address.
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公开(公告)号：US11468797B2
公开(公告)日：2022-10-11
申请号：US16911342
申请日：2020-06-24
发明人： Ishai Ilani , Noam Weber
摘要： Disclosed herein is an apparatus for calculating a cryptographic component R2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises an arithmetic logic unit configured to iteratively perform Montgomery multiplication of a first operand with a second operand to produce an intermediate result, wherein the first operand and the second operand are set to the intermediate result after each iteration, responsive to a termination condition being met, determine an adjustment parameter indicative of a difference between the intermediate result and the cryptographic component, and perform Montgomery multiplication of the intermediate result with the adjustment parameter, to calculate the cryptographic component for the cryptographic function.
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公开(公告)号：US10439644B2
公开(公告)日：2019-10-08
申请号：US15821382
申请日：2017-11-22
发明人： Ishai Ilani
摘要： A decoder configured to decode a representation of the codeword includes an error locator polynomial generator circuit. The error locator polynomial circuit is configured to generate an error locator polynomial based on a decode operation that includes iteratively adjusting values of a first polynomial, a second polynomial, a third polynomial, and a fourth polynomial. The error locator polynomial circuit is also configured to initialize the third polynomial based on even-indexed coefficients of a syndrome polynomial and initialize the fourth polynomial based on odd-indexed coefficients of the syndrome polynomial.
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公开(公告)号：US10698839B2
公开(公告)日：2020-06-30
申请号：US15962766
申请日：2018-04-25
发明人： Ishai Ilani , Eran Sharon
摘要： Apparatuses, systems, methods, and computer program products are disclosed for seed scrambling. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes an input circuit that receives a random seed. A scrambler component includes a matrix circuit that generates a new seed based on a matrix operation performed on a seed. A scrambler component includes a rotation circuit that forms a shifted seed. A shifted seed is formed by shifting a new seed based on a seed.
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公开(公告)号：US10097208B2
公开(公告)日：2018-10-09
申请号：US15456648
申请日：2017-03-13
发明人： Ishai Ilani , Idan Alrod
摘要： A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.
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公开(公告)号：US11508263B2
公开(公告)日：2022-11-22
申请号：US16911356
申请日：2020-06-24
发明人： Ishai Ilani , Noam Weber
摘要： Disclosed herein is an apparatus for calculating a cryptographic component R2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises a processor configured to set a start value to be equal to R mod n, perform b iterations of a shift and subtract operation on the start value to produce a base value, wherein the start value is set to be equal to the base value after each iteration, set a multiplication operand to be equal to the base value, and perform k iterations of a Montgomery modular multiplication of the multiplication operand with the multiplication operand to produce an intermediate result, wherein the multiplication operand is set to be equal to the intermediate result after each iteration, wherein the shift and subtract operation comprises determining a shifted start value which is equivalent to the start value multiplied by two, and subtracting n from the shifted start value if the shifted start value is greater than or equal to n.
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公开(公告)号：US11494097B2
公开(公告)日：2022-11-08
申请号：US17210174
申请日：2021-03-23
发明人： Shay Benisty , Ishai Ilani
摘要： The present disclosure generally relates to data storage devices and related methods that use secure host memory buffers (HMBs) and low latency operations. A controller of the data storage device is configured to access the HMB, where the HMB stores a Merkle Tree. When the HMB is initialized, the controller determines a number of hash levels of the Merkle Tree. Each hash level of the Merkle Tree comprises one or more hashes. When storing location data in a target data block of the Merkle Tree, the controller is configured to initialize only the hashes along a path between a top hash and the target data block. Each hash along the path has a non-initialized hash coupled to a common hash. The non-initialized hash is programmed with a non-initialized bit, such that only the relevant hashes and data blocks are initialized.
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公开(公告)号：US11152958B2
公开(公告)日：2021-10-19
申请号：US16909794
申请日：2020-06-23
发明人： Ishai Ilani
摘要： A data storage device has a controller that is configured to generate SECDED codes based on a plurality (at least 2) of codes, where each of the constituent codes is a cyclic code over a finite field of size 2m for some integer m. Any 2 constituent codes are associated with 2m1 and 2m2, where m1 and m2 are coprime (i.e., gcd(m1,m2)=1) where gcd is the greatest common divisor. In such a case, it is possible to generate a cyclic code of length (2m1−1)*(2m2−1), which will be a long code, but enjoy the complexity, in encoding and decoding, of the small fields of the constituent codes.
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公开(公告)号：US10536172B2
公开(公告)日：2020-01-14
申请号：US15817535
申请日：2017-11-20
发明人： Ishai Ilani , Idan Alrod , Eran Sharon , Mai Ghaly
摘要： A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.
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公开(公告)号：US10461777B2
公开(公告)日：2019-10-29
申请号：US15373313
申请日：2016-12-08
发明人： Ishai Ilani , Kiran Kumar Gunnam
IPC分类号： H03M13/15
摘要： An apparatus includes a convergence detector circuit coupled to an error locator polynomial generator circuit. The convergence detector circuit includes at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes. Each of the different sets of syndromes corresponds to a different one of the convergence signals.
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