公开(公告)号：US20120298965A1

公开(公告)日：2012-11-29

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/772 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US20120132989A1

公开(公告)日：2012-05-31

申请号：US12955388

申请日：2010-11-29

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

公开(公告)号：US09099327B2

公开(公告)日：2015-08-04

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L29/417

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US08936978B2

公开(公告)日：2015-01-20

申请号：US12955388

申请日：2010-11-29

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/06 ,  H01L29/417

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

公开(公告)号：US08492899B2

公开(公告)日：2013-07-23

申请号：US12904597

申请日：2010-10-14

申请人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Xiaoyan Shao

发明人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Xiaoyan Shao

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L21/44

CPC分类号： H01L21/324 ,  H01L21/28518 ,  H01L21/2885 ,  H01L31/022425 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.

摘要翻译： 本公开涉及通过在硅衬底上电沉积Ni膜而在硅表面上提供Ni硅化物金属接触的改进方法。 改进的方法导致可控硅化物形成，其中硅化物具有均匀的厚度。 金属触点可以结合在例如CMOS器件，MEM（微电机械）器件和光伏电池中。

公开(公告)号：US08293643B2

公开(公告)日：2012-10-23

申请号：US12819634

申请日：2010-06-21

申请人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L21/477

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US20130001784A1

公开(公告)日：2013-01-03

申请号：US13611363

申请日：2012-09-12

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L23/48

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US20110309508A1

公开(公告)日：2011-12-22

申请号：US12819634

申请日：2010-06-21

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US08519260B2

公开(公告)日：2013-08-27

申请号：US12832375

申请日：2010-07-08

申请人： John M. Cotte ,  Laura L. Kosbar ,  Deborah A. Neumayer ,  Xiaoyan Shao

发明人： John M. Cotte ,  Laura L. Kosbar ,  Deborah A. Neumayer ,  Xiaoyan Shao

IPC分类号： H01L31/0236

CPC分类号： H01L31/02168 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.

公开(公告)号：US08344351B2

公开(公告)日：2013-01-01

申请号：US13159594

申请日：2011-06-14

申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Alejandro G. Schrott ,  Xiaoyan Shao

发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Alejandro G. Schrott ,  Xiaoyan Shao

IPC分类号： H01L29/04 ,  H01L47/00 ,  H01L29/06

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1683 ,  H01L45/1691

摘要： A phase change memory device includes a plurality of memory cells comprising a substrate having a contact surface with an array of conductive contacts to be connected with access circuitry and a nitride layer formed at the contact surface. A plurality of vias are formed through the nitride layer to the contact surface and correspond to each conductive contact, the vias including a conformal conductive seed layer lining each via along exposed portions of the nitride layer and the contact surface and having oxidized edges. A dielectric layer is recessed within the conformal conductive seed layer and exposes a center region of each via. A phase change material is recessed within the center region of each via. A conductive material that remains conductive upon oxidation is formed over the phase change material. A top electrode is formed on each memory cell.

摘要翻译： 相变存储器件包括多个存储单元，其包括具有与要与接触电路连接的导电触点阵列的接触表面的衬底和在接触表面形成的氮化物层。 多个通孔通过氮化物层形成到接触表面并且对应于每个导电接触，通孔包括沿着氮化物层和接触表面的暴露部分并且具有氧化边缘的每个通孔衬里的共形导电种子层。 电介质层凹入保形导电晶种层内并露出每个通孔的中心区域。 相变材料凹陷在每个通孔的中心区域内。 在相变材料上形成氧化时保持导电的导电材料。 在每个存储单元上形成顶部电极。