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664 条记录 (耗时 0.025 秒)

    Radiation detecting system
    1.
    发明授权
    Radiation detecting system 失效
    辐射检测系统

    公开(公告)号：US06969859B2

    公开(公告)日：2005-11-29

    申请号：US10249872

    申请日：2003-05-14

    申请人： William A. Klaasen ,  Edward J. Nowak ,  Norman J. Rohrer

    发明人： William A. Klaasen ,  Edward J. Nowak ,  Norman J. Rohrer

    IPC分类号： G01T1/15 ,  G01T1/17 ,  G01T1/24

    CPC分类号： G01T1/17

    摘要： A radiation detecting system including a radiation detecting section having one or more radiation detecting circuits and a circuit adjustment section for adjusting other circuitry to be protected. Radiation detecting circuits are provided to detect a pulse of radiation and/or a total radiation dose accumulation.

    摘要翻译： 一种辐射检测系统，包括具有一个或多个辐射检测电路的辐射检测部分和用于调节要被保护的其它电路的电路调整部分。 提供辐射检测电路以检测辐射脉冲和/或总辐射剂量累积。

    Silicon-on-insulator latch-up pulse-radiation detector
    2.
    发明授权
    Silicon-on-insulator latch-up pulse-radiation detector 有权
    绝缘体上电锁存脉冲辐射检测器

    公开(公告)号：US06995376B2

    公开(公告)日：2006-02-07

    申请号：US10604204

    申请日：2003-07-01

    申请人： Peter E. Cottrell ,  Robert H. Dennard ,  Edward J. Nowak ,  Norman J. Rohrer

    发明人： Peter E. Cottrell ,  Robert H. Dennard ,  Edward J. Nowak ,  Norman J. Rohrer

    IPC分类号： G01T1/24

    CPC分类号： H01L31/1113

    摘要： A radiation detector formed using silicon-on-insulator technology. The radiation detector includes a silicon layer formed on an insulating substrate, wherein the silicon layer includes a PNPN structure, and a gate layer formed over the PNPN structure, wherein the gate layer includes a PN gate. Latch-up occurs in the radiation detector only in response to incident radiation.

    摘要翻译： 使用绝缘体上硅技术形成的放射线检测器。 放射线检测器包括形成在绝缘基板上的硅层，其中硅层包括PNPN结构，以及形成在PNPN结构上的栅极层，其中栅极层包括PN栅极。 仅在响应入射辐射的情况下，在辐射探测器中发生锁定。

    Body-contacted and double gate-contacted differential logic circuit and method of operation
    3.
    发明授权
    Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
    身体接触和双门接触差分逻辑电路及其操作方法

    公开(公告)号：US06580293B1

    公开(公告)日：2003-06-17

    申请号：US09683325

    申请日：2001-12-14

    申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

    IPC分类号： H03K19096

    CPC分类号： H03K19/1737 ,  H03K3/356113 ,  H03K19/0963

    摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

    摘要翻译： 设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。 逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。 在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。 在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。 结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

    Dense multi-gated device design
    4.
    发明授权
    Dense multi-gated device design 失效
    密集的多门控设备设计

    公开(公告)号：US06433372B1

    公开(公告)日：2002-08-13

    申请号：US09527863

    申请日：2000-03-17

    申请人： Eric Adler ,  Kerry Bernstein ,  John J. Ellis-Monaghan ,  Jenifer E. Lary ,  Edward J. Nowak ,  Norman J. Rohrer

    发明人： Eric Adler ,  Kerry Bernstein ,  John J. Ellis-Monaghan ,  Jenifer E. Lary ,  Edward J. Nowak ,  Norman J. Rohrer

    IPC分类号： H01L2972

    CPC分类号： H01L29/66484

    摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.

    摘要翻译： 具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。 通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层 绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。

    Transient gate tunneling current control
    5.
    发明授权
    Transient gate tunneling current control 有权
    瞬态栅极隧道电流控制

    公开(公告)号：US06577178B1

    公开(公告)日：2003-06-10

    申请号：US10064504

    申请日：2002-07-23

    申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Edward J. Nowak ,  Norman J. Rohrer ,  Douglas W. Stout

    发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Edward J. Nowak ,  Norman J. Rohrer ,  Douglas W. Stout

    IPC分类号： H03K1730

    CPC分类号： H03K19/00361 ,  H03K19/0948

    摘要： A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors. The RC structure includes a capacitor connected to a gate of the first set of transistors and a resistor connected to the capacitor and to ground.

    摘要翻译： 电路包括连接到第一组晶体管的电阻 - 电容（RC）结构和执行与第一组晶体管相同的逻辑功能的第二组晶体管。 第一组晶体管具有比第二组晶体管更薄的栅极氧化物。 RC结构从第一组晶体管引出电场，使得第一组晶体管仅在初始晶体管切换期间导通。 换句话说，在晶体管切换完成之后，RC结构关闭第一组晶体管。 此外，第一组晶体管和第二组晶体管共享公共输入和输出。 第一组晶体管表现出比第二组晶体管更高的隧穿电流。 第一组晶体管的较薄的栅极氧化物导致第一组晶体管表现出比第二组晶体管更高的器件电流。 RC结构包括连接到第一组晶体管的栅极的电容器和连接到电容器并接地的电阻器。

    Circuit for controlling the slew rate of a digital signal
    6.
    发明授权
    Circuit for controlling the slew rate of a digital signal 失效
    用于控制数字信号的转换速率的电路

    公开(公告)号：US06191628B1

    公开(公告)日：2001-02-20

    申请号：US09224763

    申请日：1999-01-04

    申请人： Kerry Bernstein ,  Edward J. Nowak ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Edward J. Nowak ,  Norman J. Rohrer

    IPC分类号： H03K512

    CPC分类号： H03K19/00323 ,  H03K5/131 ,  H03K5/133 ,  H03K19/00361 ,  H03K2005/00071

    摘要： A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.

    摘要翻译： 用于选择性地控制数据线上的信号的转换速率的电路。 电容器一端连接到电源的公共端子和开关电路。 开关电路有利地将电容器响应于控制脉冲连接到数据线，电容性地加载数据线，使得转换速率降低。 当控制脉冲处于不同状态时，电容器通过开关电路连接到电源的端子，并用作去耦电容器。 电容器的双重作用通过利用两个功能中的一个组件来提供有效的电路布局。

    SOI radio frequency switch with enhanced electrical isolation
    8.
    发明授权
    SOI radio frequency switch with enhanced electrical isolation 有权
    SOI射频开关具有增强的电气隔离

    公开(公告)号：US08866226B2

    公开(公告)日：2014-10-21

    申请号：US13345871

    申请日：2012-01-09

    申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

    发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

    IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L27/1203

    摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

    摘要翻译： 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。