公开(公告)号：US20130240997A1

公开(公告)日：2013-09-19

申请号：US13424319

申请日：2012-03-19

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/7843

摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。

公开(公告)号：US08492214B2

公开(公告)日：2013-07-23

申请号：US13051510

申请日：2011-03-18

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L21/338

CPC分类号： H01L31/0232 ,  G06F17/5045 ,  G06F17/5054 ,  H01L27/14632 ,  H01L27/14683 ,  H01L29/66545

摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

摘要翻译： 提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。 该方法包括在虚拟栅极结构上形成介电层。 该方法还包括在电介质层中形成一个或多个凹槽。 该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。 该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

公开(公告)号：US20120181588A1

公开(公告)日：2012-07-19

申请号：US13005650

申请日：2011-01-13

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/113 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L27/14614 ,  H01L27/14689

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.

摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。 栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。 栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。

公开(公告)号：US07736053B2

公开(公告)日：2010-06-15

申请号：US12348974

申请日：2009-01-06

申请人： William F. Clark, Jr. ,  Edward J. Nowak

发明人： William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： G01K3/06 ,  G01K7/00 ,  G01K15/00 ,  G01K17/00

CPC分类号： G01K7/015 ,  G01K7/22 ,  G01K15/00

摘要： Disclosed are embodiments of an improved on-chip temperature sensing circuit, based on bolometry, which provides self calibration of the on-chip temperature sensors for ideality and an associated method of sensing temperature at a specific on-chip location. The circuit comprises a temperature sensor, an identical reference sensor with a thermally coupled heater and a comparator. The comparator is adapted to receive and compare the outputs from both the temperature and reference sensors and to drive the heater with current until the outputs match. Based on the current forced into the heater, the temperature rise of the reference sensor can be calculated, which in this state, is equal to that of the temperature sensor.

摘要翻译： 公开了一种改进的片上温度感测电路的实施例，其基于速率测量，其提供用于理想的片上温度传感器的自校准以及在特定片上位置处感测温度的相关联的方法。 该电路包括温度传感器，具有热耦合加热器的相同参考传感器和比较器。 比较器适用于接收和比较来自温度和参考传感器的输出，并用电流驱动加热器直到输出匹配。 基于被迫进入加热器的电流，可以计算参考传感器的温度上升，在该状态下，其温度上升等于温度传感器的温升。

公开(公告)号：US20100047972A1

公开(公告)日：2010-02-25

申请号：US12610563

申请日：2009-11-02

申请人： William F. Clark, JR. ,  Edward J. Nowak

发明人： William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/861 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6609 ,  H01L29/772 ,  H01L29/78648

摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.

摘要翻译： 公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 场屏蔽被夹在晶片上的上隔离层和下隔离层之间。 局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。 因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。

公开(公告)号：US07667527B2

公开(公告)日：2010-02-23

申请号：US11561480

申请日：2006-11-20

申请人： William F. Clark, Jr. ,  Edward J. Nowak

发明人： William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H03K3/01

CPC分类号： G05F3/205

摘要： Structure and process for compensating threshold voltage variation due to process variation. The structure includes a circuit segmented into sub-blocks having a predetermined size corresponding to a characteristic length associated with a process variation. A local circuit is located in each circuit sub-block, and a reference signal coupled to each local circuit. The local circuit generates a compensation signal in response to the reference signal to adjust an electrical parameter of the respective sub-block to a predetermined value.

摘要翻译： 用于补偿由于过程变化引起的阈值电压变化的结构和过程。 该结构包括分割成具有对应于与过程变化相关联的特征长度的预定尺寸的子块的电路。 本地电路位于每个电路子块中，并且参考信号耦合到每个本地电路。 本地电路响应于参考信号产生补偿信号，以将相应子块的电参数调整到预定值。

公开(公告)号：US20090298250A1

公开(公告)日：2009-12-03

申请号：US12536636

申请日：2009-08-06

申请人： Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L21/331

CPC分类号： H01L21/84 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0804 ,  H01L29/7327 ,  H01L29/78648

摘要： A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.

摘要翻译： 公开了一种结构，其包括在体层上包括绝缘体层的衬底和在衬底的第一区域中的双极晶体管，所述双极晶体管包括绝缘体层中的发射极区域的至少一部分。 另一公开的结构包括在衬底的第一区域中的反相双极晶体管，其包括体层上的绝缘体层，反相双极晶体管包括发射极区域，以及位于衬底的第二区域中的后栅极晶体管，其中背面 背栅式晶体管的栅极导体和发射极区域的至少一部分处于相同的材料层中。 还公开了一种将双极晶体管和后栅极晶体管组合在一起的结构的方法。

公开(公告)号：US07517806B2

公开(公告)日：2009-04-14

申请号：US11186748

申请日：2005-07-21

申请人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

发明人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

IPC分类号： H01L21/302

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US20090020806A1

公开(公告)日：2009-01-22

申请号：US11778185

申请日：2007-07-16

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

公开(公告)号：US07378357B2

公开(公告)日：2008-05-27

申请号：US11264446

申请日：2005-11-01

申请人： William F. Clark, Jr. ,  Edward J. Nowak

发明人： William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.

摘要翻译： 公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。 这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。 较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。 包括与栅极电介质不同的材料的盖可以位于鳍片上方。