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    Magnetic stripe reader
    1.
    发明授权
    Magnetic stripe reader 失效
    磁条阅读器

    公开(公告)号：US07163148B2

    公开(公告)日：2007-01-16

    申请号：US10816265

    申请日：2004-03-31

    申请人： William Gene Durbin ,  Brent Wilson

    发明人： William Gene Durbin ,  Brent Wilson

    IPC分类号： G06K7/08

    CPC分类号： G06K7/084 ,  G11B5/00808 ,  G11B5/09

    摘要： A magnetic stripe card reader for reading a magnetic stripe on a card having at least one track of magnetically stored information stored thereon as a stream of encoded discrete data bits separated by bit times is disclosed. Aa magnetic head is provided for reading the magnetic pulses as the magnetic stripe is passed thereby to output a time varying analog signal. A data converter incorporated on an integrated circuit is then operable for converting the analog signal to a digital time series of digital values. A processor incorporated on the integrated circuit can ten process the digital output of the data converter and is operable to first determine potential bit boundaries and then recover timing information from the digital time series to discriminate the bit times between data bits. The value of each data bit is then determined during each bit time to provide a stream of extracted data bits.

    摘要翻译： 公开了一种磁条读卡器，用于读取具有存储在其上的磁存储信息的至少一个磁道的卡上的磁条作为由位时间分隔的编码离散数据位流。 Aa磁头被提供用于在磁条通过时读取磁脉冲，从而输出时变模拟信号。 结合在集成电路上的数据转换器然后可操作用于将模拟信号转换为数字值的数字时间序列。 集成在集成电路上的处理器可十进制数据转换器的数字输出，并可操作以首先确定潜在的位边界，然后从数字时间序列中恢复定时信息，以区分数据位之间的位时间。 然后在每个比特时间期间确定每个数据比特的值以提供提取的数据比特流。

    SYSTEM AND METHOD FOR DYNAMICALLY REGULATING VOLTAGE TO MINIMIZE POWER CONSUMPTION
    2.
    发明申请
    SYSTEM AND METHOD FOR DYNAMICALLY REGULATING VOLTAGE TO MINIMIZE POWER CONSUMPTION 有权
    用于动态调节电压以最小化功耗的系统和方法

    公开(公告)号：US20110065399A1

    公开(公告)日：2011-03-17

    申请号：US12570091

    申请日：2009-09-30

    申请人： Michael Keith Odland ,  Brent Wilson

    发明人： Michael Keith Odland ,  Brent Wilson

    IPC分类号： H04B1/04 ,  H02J1/00

    CPC分类号： H02J1/10 ,  H02J1/14 ,  Y10T307/505 ,  Y10T307/549 ,  Y10T307/653 ,  Y10T307/696

    摘要： A system includes a voltage regulator connected to a voltage source for providing a regulated voltage at a first level in a first mode of operation and at least one second level in a second mode of operation. The second voltage level is higher than the first voltage level. A control processor provides control signals to select between the first and the second modes of operation. A component associated with the voltage regulator. The component is disabled in the first mode of operation and enabled in the second mode of operation. The control processor generates control signals to configure the voltage regulator to generate the voltage at the first level in the first mode of operation when the component is disabled and to configure the voltage regulator to generate the voltage at the at least one second level in the second mode of operation when the component is enabled.

    摘要翻译： 系统包括连接到电压源的电压调节器，用于在第一操作模式中提供处于第一电平的调节电压，并在第二操作模式中提供至少一个第二电平。 第二电压电平高于第一电压电平。 控制处理器提供控制信号以在第一和第二操作模式之间进行选择。 与电压调节器相关的部件。 该组件在第一种操作模式下被禁用，并在第二种操作模式下启用。 控制处理器产生控制信号以配置电压调节器以在组件被禁用时在第一操作模式中产生处于第一电平的电压，并且配置电压调节器以在第二电平中产生至少一个第二电平的电压 启用组件时的操作模式。

    Magnetic stripe reader
    3.
    发明申请
    Magnetic stripe reader 失效
    磁条阅读器

    公开(公告)号：US20050219728A1

    公开(公告)日：2005-10-06

    申请号：US10816265

    申请日：2004-03-31

    申请人： William Durbin ,  Brent Wilson

    发明人： William Durbin ,  Brent Wilson

    IPC分类号： G06K7/08 ,  G11B5/008 ,  G11B5/09

    CPC分类号： G06K7/084 ,  G11B5/00808 ,  G11B5/09

    摘要： A magnetic stripe card reader for reading a magnetic stripe on a card having at least one track of magnetically stored information stored thereon as a stream of encoded discrete data bits separated by bit times is disclosed. Aa magnetic head is provided for reading the magnetic pulses as the magnetic stripe is passed thereby to output a time varying analog signal. A data converter incorporated on an integrated circuit is then operable for converting the analog signal to a digital time series of digital values. A processor incorporated on the integrated circuit can ten process the digital output of the data converter and is operable to first determine potential bit boundaries and then recover timing information from the digital time series to discriminate the bit times between data bits. The value of each data bit is then determined during each bit time to provide a stream of extracted data bits.

    摘要翻译： 公开了一种磁条读卡器，用于读取具有存储在其上的磁存储信息的至少一个磁道的卡上的磁条作为由位时间分隔的编码离散数据位流。 Aa磁头被提供用于在磁条通过时读取磁脉冲，从而输出时变模拟信号。 结合在集成电路上的数据转换器然后可操作用于将模拟信号转换为数字值的数字时间序列。 集成在集成电路上的处理器可十进制数据转换器的数字输出，并可操作以首先确定潜在的位边界，然后从数字时间序列中恢复定时信息，以区分数据位之间的位时间。 然后在每个比特时间期间确定每个数据比特的值以提供提取的数据比特流。

    SYSTEM AND METHOD FOR SUPPORTING HIGH BURST CURRENT IN A CURRENT LIMITED SYSTEM
    4.
    发明申请
    SYSTEM AND METHOD FOR SUPPORTING HIGH BURST CURRENT IN A CURRENT LIMITED SYSTEM 有权
    在电流有限系统中支持高电流的系统和方法

    公开(公告)号：US20110062785A1

    公开(公告)日：2011-03-17

    申请号：US12570088

    申请日：2009-09-30

    申请人： Michael Keith Odland ,  Brent Wilson

    发明人： Michael Keith Odland ,  Brent Wilson

    IPC分类号： H02J1/00

    CPC分类号： H02J1/10 ,  H02J1/14 ,  Y10T307/505 ,  Y10T307/549 ,  Y10T307/653 ,  Y10T307/696

    摘要： A current limited system for providing a burst current capability comprises a variable load having a first mode of operation requiring a first current level and a burst current mode of operation requiring a second current level. The second current level is greater than the first current level. A control processor provides control signals for the current limited system. A voltage source is connected to the variable load to provide a source current. The source current provides the variable load the first current level in the first mode of operation. A burst mode circuit provides the second current level to the variable load in the burst current mode of operation, responsive to the control signals from the control processor and the voltage source.

    摘要翻译： 用于提供突发电流能力的电流限制系统包括具有需要第一电流电平的第一操作模式和需要第二电流电平的突发电流操作模式的可变负载。 第二个当前级别大于第一个当前级别。 控制处理器为当前受限系统提供控制信号。 电压源连接到可变负载以提供源极电流。 源电流在第一种工作模式下提供可变负载的第一电流电平。 突发模式电路响应于来自控制处理器和电压源的控制信号，在突发电流操作模式中向可变负载提供第二电流电平。

    SYSTEM AND METHOD FOR MONITORING A CAPACITIVE SENSOR ARRAY
    5.
    发明申请
    SYSTEM AND METHOD FOR MONITORING A CAPACITIVE SENSOR ARRAY 审中-公开
    用于监测电容式传感器阵列的系统和方法

    公开(公告)号：US20090322410A1

    公开(公告)日：2009-12-31

    申请号：US12146352

    申请日：2008-06-25

    申请人： Thomas S. David ,  Brian Caloway ,  Golam Chowdhury ,  Brent Wilson ,  Farris Bar ,  Douglas Piasecki

    发明人： Thomas S. David ,  Brian Caloway ,  Golam Chowdhury ,  Brent Wilson ,  Farris Bar ,  Douglas Piasecki

    IPC分类号： G06F3/044

    CPC分类号： G06F3/044 ,  G06F3/0412 ,  G06F3/0416

    摘要： A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes.

    摘要翻译： 电容式触摸传感器电路包括用于与连接到电容式传感器阵列的行和列的多个I / O引脚互连的接口。 响应于来自多个I / O引脚的输入的监控电路确定电容式传感器阵列中的电容开关何时已被致动并且存储电容开关的致动指示。 监控电路然后响应所确定的致动产生中断。 控制引擎控制监视电路监视多个I / O引脚的方式。 控制引擎和监控电路可以被配置为以多种操作模式监视多个I / O引脚。

    Method and apparatus for calibration of a low frequency oscillator in a processor based system
    6.
    发明申请
    Method and apparatus for calibration of a low frequency oscillator in a processor based system 有权
    用于在基于处理器的系统中校准低频振荡器的方法和装置

    公开(公告)号：US20050270108A1

    公开(公告)日：2005-12-08

    申请号：US10865110

    申请日：2004-06-10

    申请人： Brent Wilson ,  Paul Highley ,  Kenneth Fernald

    发明人： Brent Wilson ,  Paul Highley ,  Kenneth Fernald

    IPC分类号： H03B1/00 ,  H03L1/02 ,  H03L7/08

    CPC分类号： H03L7/08 ,  H03L1/02

    摘要： Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

    摘要翻译： 用于在基于处理器的系统中校准低频振荡器的方法和装置。 一种用于校准片上非精密振荡器的方法。 提供具有在可接受的工作公差内的已知操作频率的片上精密振荡器。 片上精密振荡器用作时基，然后根据时基测量片上振荡器的周期。 然后确定片上非精密振荡器的测量频率与片上非精密振荡器的期望工作频率之间的差异。 在确定差异之后，调整片上非精密振荡器的频率以使确定的差最小化。

    Visual dynamic range timestamp to enhance data coherency and potential of metadata using delay information
    7.
    发明授权
    Visual dynamic range timestamp to enhance data coherency and potential of metadata using delay information 有权
    视觉动态范围时间戳，以增强数据一致性和使用延迟信息的元数据的潜力

    公开(公告)号：US09549197B2

    公开(公告)日：2017-01-17

    申请号：US13195300

    申请日：2011-08-01

    申请人： Neil W. Messmer ,  Brent Wilson

    发明人： Neil W. Messmer ,  Brent Wilson

    IPC分类号： H04N7/00 ,  H04N19/467 ,  H04N21/84

    CPC分类号： H04N19/467 ,  H04N21/84

    摘要： A system and method for enhancing data coherency and potential of at least one metadata associated with a video data configured to operate in a visual dynamic range (VDR) format are detailed. One system embodiment employs a metadata framing structure which includes a header start of frame bit set, a packet type bit set, a configuration bit set, a variable depth configuration/metadata bit set, a header end of frame bit set, a timestamp bit set for specifying a frame delay count to apply the at least one metadata to the video data and a checksum check bit set. The at least one metadata is designed to embed within a code word guard bit position of at least one color channel of the video data and adaptable to embed within the VDR pipeline to enhance the quality of the video data.

    摘要翻译： 详细描述了一种用于增强数据一致性的系统和方法，以及配置成以视觉动态范围（VDR）格式操作的视频数据相关联的至少一个元数据的潜力。 一个系统实施例采用元数据成帧结构，其包括帧位集合的报头开始，分组类型位集合，配置位集合，可变深度配置/元数据位集合，帧位集合的报头结束，时间戳位集合 用于指定帧延迟计数以将至少一个元数据应用于视频数据和校验和校验位集合。 至少一个元数据被设计成嵌入在视频数据的至少一个颜色通道的代码字保护位位置中，并且可适应于嵌入在VDR流水线内以增强视频数据的质量。

    System and method for dynamically regulating voltage to minimize power consumption
    9.
    发明授权
    System and method for dynamically regulating voltage to minimize power consumption 有权
    用于动态调节电压的系统和方法以最小化功耗

    公开(公告)号：US08620237B2

    公开(公告)日：2013-12-31

    申请号：US12570091

    申请日：2009-09-30

    申请人： Keith Odland ,  Brent Wilson

    发明人： Keith Odland ,  Brent Wilson

    IPC分类号： H01Q11/12

    CPC分类号： H02J1/10 ,  H02J1/14 ,  Y10T307/505 ,  Y10T307/549 ,  Y10T307/653 ,  Y10T307/696

    摘要： A system includes a voltage regulator connected to a voltage source for providing a regulated voltage at a first level in a first mode of operation and at least one second level in a second mode of operation. The second voltage level is higher than the first voltage level. A control processor provides control signals to select between the first and the second modes of operation. A component associated with the voltage regulator. The component is disabled in the first mode of operation and enabled in the second mode of operation. The control processor generates control signals to configure the voltage regulator to generate the voltage at the first level in the first mode of operation when the component is disabled and to configure the voltage regulator to generate the voltage at the at least one second level in the second mode of operation when the component is enabled.

    摘要翻译： 系统包括连接到电压源的电压调节器，用于在第一操作模式中提供处于第一电平的调节电压，并在第二操作模式中提供至少一个第二电平。 第二电压电平高于第一电压电平。 控制处理器提供控制信号以在第一和第二操作模式之间进行选择。 与电压调节器相关的部件。 该组件在第一种操作模式下被禁用，并在第二种操作模式下启用。 控制处理器产生控制信号以配置电压调节器以在组件被禁用时在第一操作模式中产生处于第一电平的电压，并且配置电压调节器以在第二电平中产生至少一个第二电平的电压 启用组件时的操作模式。

    Scorecard Interface Editor
    10.
    发明申请
    Scorecard Interface Editor 有权
    记分卡界面编辑器

    公开(公告)号：US20090106640A1

    公开(公告)日：2009-04-23

    申请号：US11877127

    申请日：2007-10-23

    申请人： Stephen Van de Walker Handy ,  Peter Birkedal Peterson ,  Brent Wilson ,  Corey J. Hulen

    发明人： Stephen Van de Walker Handy ,  Peter Birkedal Peterson ,  Brent Wilson ,  Corey J. Hulen

    IPC分类号： G06F17/24

    CPC分类号： G06Q10/00 ,  G06Q10/0639 ,  G06Q10/06393

    摘要： A user interface is programmed to create a scorecard. The interface includes a scorecard module including a column area and a row area, and a key performance indicator area including a plurality of key performance indicators. A key performance indicator from the key performance indicator area can be dragged and dropped onto one of the column area and the row area to add indicia associated with the key performance indicator to the scorecard.

    摘要翻译： 编程用户界面创建记分卡。 该接口包括包括列区域和行区域的记分卡模块以及包括多个关键性能指标的关键性能指标区域。 关键性能指标区域的关键性能指标可以拖放到列区域和行区域之一，以将与关键性能指标相关联的标记添加到记分卡。