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1.发明授权Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法公开(公告)号：US06436749B1
公开(公告)日：2002-08-20
申请号：US09658655
申请日：2000-09-08
申请人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
发明人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823842
摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.
摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。
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公开(公告)号：US6111425A
公开(公告)日：2000-08-29
申请号：US173436
申请日：1998-10-15
IPC分类号： H03K19/003 , H03K3/356 , H03K19/173 , H03K17/16
CPC分类号： H03K3/356113 , H03K19/1738
摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
摘要翻译： 一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。 在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。 本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。 在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。 第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。
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3.发明授权Logic SOI structure, process and application for vertical bipolar transistor 有权逻辑SOI结构，工艺和应用于垂直双极晶体管公开(公告)号：US06790722B1
公开(公告)日：2004-09-14
申请号：US09718850
申请日：2000-11-22
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L218238
CPC分类号： H01L29/66265 , H01L21/8249 , H01L27/0623 , H01L29/7317
摘要： A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
摘要翻译： 用于在垂直双极晶体管中形成发射极的方法和结构包括在集电极层上提供具有集电极层和基极层的衬底，在集电极层上形成图案掩模，并在发光体材料中填充掩模中的开口 大马士革过程。 CMOS /垂直双极结构具有彼此垂直设置的集电极，基极区域和发射极区域，集电极区域具有与衬底间隔离氧化物相邻的峰值掺杂剂浓度。
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公开(公告)号：US06498518B1
公开(公告)日：2002-12-24
申请号：US09617680
申请日：2000-07-14
IPC分类号： H03K522
CPC分类号： H04L25/0292 , H03K5/24 , H03K19/017554
摘要： A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.
摘要翻译： 连接到电源端子并且具有至少一个输入端子和至少一个输出端子的电流感测电路包括至少一个具有基极，发射极和集电极的双极晶体管，连接到电源端子的至少一个电流镜放大器， 所述电流镜放大器具有连接到所述集电极并且具有连接到所述发射极的至少一个输出的输入端和连接到所述基极的DC电压源。
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公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译： 一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。 当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。 低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。 选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。 或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。
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公开(公告)号：US6097241A
公开(公告)日：2000-08-01
申请号：US159898
申请日：1998-09-24
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.
摘要翻译： 诸如具有独立阈值电压控制的具有分区功能单元的ASIC器件的集成电路。 第一分区总是以正常模式操作，而后续分区保持在待机模式，直到在第一分区的输入处检测到转换。 随后的分区通过降低施加到每个分区的设备的体电压而切换到正常模式。 在检测到转换之后，使用脉冲展开器将分区保持在正常模式下预定的时间段。
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7.发明授权公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译： 一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。 该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。
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公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译： 提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。 优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。 本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个 输出驱动器响应于该结点的合成波形。
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公开(公告)号：US06437385B1
公开(公告)日：2002-08-20
申请号：US09607094
申请日：2000-06-29
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L28/55 , H01L28/87 , H01L29/66181 , H01L29/945
摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.
摘要翻译： 对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。 这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。 阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。
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10.发明授权公开(公告)号：US06281731B1
公开(公告)日：2001-08-28
申请号：US09428639
申请日：1999-10-27
IPC分类号： H03K3297
CPC分类号： H03K3/3565 , H03K3/02337
摘要： A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.
摘要翻译： 差分接收器具有根据参考电压精确设置的开关点，通过差分接收器内部的电路动态地修改切换点，即提供直流滞后。 通过在差分接收器的输入晶体管和参考晶体管之间建立背栅电压差来调整所产生的关于参考信号的滞后特性的定位。 还提供了一种开关电路，用于控制滞后电路在参考信号加或减所需偏移的切换。 开关电路由输入晶体管的输出信号选通。
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