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    Signal detect for high-speed serial interface
    1.
    发明授权
    Signal detect for high-speed serial interface 有权
    信号检测用于高速串行接口

    公开(公告)号：US08290750B1

    公开(公告)日：2012-10-16

    申请号：US13036437

    申请日：2011-02-28

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    IPC分类号： H03F1/26

    CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

    摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

    摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

    Apparatus and methods for low-jitter transceiver clocking
    2.
    发明授权
    Apparatus and methods for low-jitter transceiver clocking 有权
    低抖动收发器时钟的装置和方法

    公开(公告)号：US08406258B1

    公开(公告)日：2013-03-26

    申请号：US12752984

    申请日：2010-04-01

    申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    IPC分类号： H04J3/06

    CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

    摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。

    Signal detect for high-speed serial interface
    4.
    发明授权
    Signal detect for high-speed serial interface 有权
    信号检测用于高速串行接口

    公开(公告)号：US07899649B1

    公开(公告)日：2011-03-01

    申请号：US12053884

    申请日：2008-03-24

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    IPC分类号： G06F19/00

    CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

    摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

    摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

    High-speed serial data signal interface architectures for programmable logic devices
    5.
    发明授权
    High-speed serial data signal interface architectures for programmable logic devices 有权
    用于可编程逻辑器件的高速串行数据信号接口架构

    公开(公告)号：US07860203B1

    公开(公告)日：2010-12-28

    申请号：US11725653

    申请日：2007-03-19

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

    IPC分类号： H04L7/00

    CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

    摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

    摘要翻译： 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE
    6.
    发明申请
    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
    用于可编程逻辑器件高速串行接口的信号丢失检测器

    公开(公告)号：US20090011716A1

    公开(公告)日：2009-01-08

    申请号：US11773234

    申请日：2007-07-03

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04Q7/20

    CPC分类号： H04L25/45

    摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

    摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE
    7.
    发明申请
    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
    用于可编程逻辑器件高速串行接口的信号丢失检测器

    公开(公告)号：US20110235756A1

    公开(公告)日：2011-09-29

    申请号：US13151717

    申请日：2011-06-02

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04L27/06

    CPC分类号： H04L25/45

    摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

    摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

    Power supply filtering for programmable logic device having heterogeneous serial interface architecture
    8.
    发明授权
    Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
    具有异构串行接口架构的可编程逻辑器件的电源滤波

    公开(公告)号：US07903679B1

    公开(公告)日：2011-03-08

    申请号：US11622396

    申请日：2007-01-11

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04L12/56

    CPC分类号： H03K19/17744

    摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

    摘要翻译： 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

    Integrated circuit architectures with heterogeneous high-speed serial interface circuitry
    9.
    发明授权
    Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
    具有异构高速串行接口电路的集成电路架构

    公开(公告)号：US07759972B1

    公开(公告)日：2010-07-20

    申请号：US11981934

    申请日：2007-10-31

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H01L25/00

    CPC分类号： H03K19/177

    摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。 这些传统块离开设备的至少一个角落，不被这种遗留电路占用。 这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。 相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links
    10.
    发明授权
    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权
    信号幅度检测电路，无高速串行链路的模式相关性

    公开(公告)号：US07576570B1

    公开(公告)日：2009-08-18

    申请号：US11508607

    申请日：2006-08-22

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153 ,  H03K5/24

    摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

    摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。