公开(公告)号：US07742315B2

公开(公告)日：2010-06-22

申请号：US11282041

申请日：2005-11-17

申请人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Gerald J. Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

发明人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Gerald J. Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K1/11 ,  H01R12/523 ,  H01R13/6466 ,  H01R13/6471 ,  H01R13/6589 ,  H01R13/6625 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/10189

摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

摘要翻译： 本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。 特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。 为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容 在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

公开(公告)号：US07355125B2

公开(公告)日：2008-04-08

申请号：US11281688

申请日：2005-11-17

申请人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

发明人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC分类号： H05K1/03

CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure whereina) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, andb) a signal layer being located adjacent to said reference planes.

摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US20080225484A1

公开(公告)日：2008-09-18

申请号：US11687037

申请日：2007-03-16

申请人： William L. Brodsky ,  Peter J. Brofman ,  James A. Busby ,  Bruce J. Chamberlin ,  Scott A. Cummings ,  David L. Edwards ,  Thomas J. Fleischman ,  Michael J. Griffin ,  Sushumna Iruvanti ,  David C. Long ,  Jennifer V. Muncy ,  Robin A. Susko

发明人： William L. Brodsky ,  Peter J. Brofman ,  James A. Busby ,  Bruce J. Chamberlin ,  Scott A. Cummings ,  David L. Edwards ,  Thomas J. Fleischman ,  Michael J. Griffin ,  Sushumna Iruvanti ,  David C. Long ,  Jennifer V. Muncy ,  Robin A. Susko

IPC分类号： H05K7/20

CPC分类号： H01L23/42 ,  H01L23/433 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2224/0401

摘要： Methods, apparatus and assemblies for enhancing heat transfer in electronic components using a flexible thermal pillow. The flexible thermal pillow has a thermally conductive material sealed between top and bottom conductive layers, with the bottom layer having a flexible reservoir residing on opposing sides of a central portion of the pillow that has a gap. The pillow may have roughened internal surfaces to increase an internal surface area within the pillow for enhanced heat dissipation. In an electronic assembly, the central portion of the pillow resides between a heat sink and heat-generating component for the thermal coupling there-between. During thermal cycling, the flexible reservoir of the pillow expands to retain thermally conductive material extruded from the gap, and then contracts to force such extruded material back into the gap. An external pressure source may contact the pillow for further forcing the extruded thermally conductive material back into the gap.

摘要翻译： 使用柔性热枕头增强电子部件传热的方法，装置和组件。 柔性热枕头具有密封在顶部和底部导电层之间的导热材料，底层具有位于枕头的中心部分的具有间隙的相对侧上的柔性容器。 枕头可能具有粗糙的内表面以增加枕头内的内表面积，以增强散热。 在电子组件中，枕头的中心部分位于散热器和用于其之间的热耦合的发热部件之间。 在热循环期间，枕头的柔性储存器膨胀以保持从间隙挤出的导热材料，然后收缩以迫使这种挤出的材料回到间隙中。 外部压力源可以接触枕头，以进一步迫使挤出的导热材料回到间隙中。

公开(公告)号：US20080142249A1

公开(公告)日：2008-06-19

申请号：US11610470

申请日：2006-12-13

申请人： Bruce J. Chamberlin ,  Daniel N. De Araujo ,  Erica E. Jasper Gant ,  Bhyrav M. Mutnury

发明人： Bruce J. Chamberlin ,  Daniel N. De Araujo ,  Erica E. Jasper Gant ,  Bhyrav M. Mutnury

IPC分类号： H05K1/02 ,  H05K3/00

CPC分类号： H05K1/0242 ,  H05K3/384 ,  H05K3/4611 ,  H05K2201/09972 ,  Y10T29/49155

摘要： A circuit board and a method for fabricating a circuit board are provided. The circuit board includes a dielectric core comprising a first surface and a second surface and a conductive layer comprising a first surface and a second surface. The first surface of the conductive layer is coupled to the second surface of the dielectric core. A first region of the second surface of the conductive layer is smooth and a second region of the second surface of the conductive layer is rough. The first region of the second surface of the conductive layer is operable to support high speed signaling and the second region of the second surface of the conductive layer is operable to support non-high speed signaling.

摘要翻译： 提供电路板和制造电路板的方法。 该电路板包括一个包括一个第一表面和一个第二表面的电介质芯，以及一个包括第一表面和第二表面的导电层。 导电层的第一表面耦合到介质芯的第二表面。 导电层的第二表面的第一区域是光滑的，并且导电层的第二表面的第二区域是粗糙的。 导电层的第二表面的第一区可操作以支持高速信号，并且导电层的第二表面的第二区可操作以支持非高速信号。

公开(公告)号：US06894228B2

公开(公告)日：2005-05-17

申请号：US10217674

申请日：2002-08-12

申请人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

发明人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01L23/538 ,  H05K1/02 ,  H05K3/46

CPC分类号： H01L23/5383 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/0265 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/1581 ,  H01L2924/00

摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

摘要翻译： 一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。 密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路 必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。 本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。

公开(公告)号：US07109722B2

公开(公告)日：2006-09-19

申请号：US10865598

申请日：2004-06-10

申请人： Bruce J. Chamberlin ,  Prabjit Singh ,  Timothy M. Trifilo

发明人： Bruce J. Chamberlin ,  Prabjit Singh ,  Timothy M. Trifilo

IPC分类号： H01H31/12

CPC分类号： H05K1/0256 ,  H05K1/0268 ,  H05K1/111 ,  H05K2201/0761 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/163

摘要： An apparatus and method for at least one of detecting and preventing burning of a PCB is disclosed. The method includes configuring a first comb array defined by a plurality of first fingers at a first potential; configuring a second comb array defined by a plurality of second fingers at a second potential different from the first potential; interlacing the plurality of first fingers defining the first comb array with the plurality of second fingers defining the second comb array embedded in a substrate; disposing the substrate with the PCB; and detecting a rise in leakage current between the first and second comb arrays indicative of a breakdown of the substrate.

摘要翻译： 公开了一种用于检测和防止PCB燃烧中的至少一种的装置和方法。 该方法包括：以第一电位配置由多个第一手指定义的第一梳状阵列; 以不同于所述第一电位的第二电位配置由多个第二指状物限定的第二梳状阵列; 将限定第一梳状阵列的多个第一手指与限定嵌入基底中的第二梳状阵列的多个第二指状物交错; 用PCB布置基板; 以及检测第一和第二梳状阵列之间的泄漏电流的上升，指示衬底的击穿。

公开(公告)号：US06426466B1

公开(公告)日：2002-07-30

申请号：US09501480

申请日：2000-02-09

申请人： Bruce J. Chamberlin ,  John M. Lauffer ,  James R. Stack

发明人： Bruce J. Chamberlin ,  John M. Lauffer ,  James R. Stack

IPC分类号： H05K102

CPC分类号： H05K1/0263 ,  H01R12/7088 ,  H05K3/325 ,  H05K3/403 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/10272 ,  H05K2201/2018

摘要： A printed wiring board structure having peripheral power input. A printed wiring board having internal conductive layers, wherein each internal conductive layer contains a plurality of tabs extending therefrom. Tabs of similar voltage are vertically aligned within the printed wiring board. A frame within which the printed wiring board is mounted is also provided. The frame, having connections mounted within an inner surface of the frame, electrically contacts the tabs along the periphery of the printed wiring board.

摘要翻译： 具有外围电源输入的印刷电路板结构。 一种具有内部导电层的印刷线路板，其中每个内部导电层包含从其延伸的多个翼片。 类似电压的标签在印刷电路板内垂直对齐。 还提供了安装印刷电路板的框架。 具有安装在框架的内表面内的连接的框架沿着印刷线路板的周边与接片电接触。

公开(公告)号：US20090057865A1

公开(公告)日：2009-03-05

申请号：US11847606

申请日：2007-08-30

申请人： William L. Brodsky ,  James A. Busby ,  Bruce J. Chamberlin ,  Mitchell G. Ferrill ,  David L. Questad ,  Robin A. Susko

发明人： William L. Brodsky ,  James A. Busby ,  Bruce J. Chamberlin ,  Mitchell G. Ferrill ,  David L. Questad ,  Robin A. Susko

IPC分类号： H01L23/22 ,  H01L21/54 ,  H01L23/24

CPC分类号： H01L23/3121 ,  H01L23/4006 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2023/4081 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/05599

摘要： An LGA structure is provided having at least one semiconductor device over a substrate and a mechanical load apparatus over the semiconductor device. The structure includes a load-distributing material between the mechanical load apparatus and the substrate. Specifically, the load-distributing material is proximate a first side of the semiconductor device and a second side of the semiconductor device opposite the first side of the semiconductor device. Furthermore, the load-distributing material completely surrounds the semiconductor device and contacts the mechanical load apparatus, the substrate, and the semiconductor device. The load-distributing material can be thermally conductive and comprises an elastomer and/or a liquid. The load-distributing material comprises a LGA interposer adapted to connect the substrate to a PCB below the substrate and/or a second substrate. Moreover, the load-distributing material comprises compressible material layers and rigid material layers. The load-distributing material comprises a rigid material incased in a compressible material.

摘要翻译： 提供LGA结构，其具有在衬底上的至少一个半导体器件和半导体器件上的机械负载设备。 该结构包括在机械负载装置和基板之间的负载分配材料。 具体地，负载分布材料靠近半导体器件的第一侧，并且半导体器件的与半导体器件的第一侧相对的第二侧。 此外，负载分布材料完全围绕半导体器件并接触机械负载装置，衬底和半导体器件。 载荷分布材料可以是导热的并且包括弹性体和/或液体。 负载分配材料包括适于将衬底连接到衬底下面的PCB和/或第二衬底的LGA插入器。 此外，载荷分布材料包括可压缩材料层和刚性材料层。 载荷分配材料包括浸在可压缩材料中的刚性材料。

公开(公告)号：US06407341B1

公开(公告)日：2002-06-18

申请号：US09557802

申请日：2000-04-25

申请人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich ,  Douglas O. Powell ,  Joseph P. Resavy ,  James R. Stack

发明人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich ,  Douglas O. Powell ,  Joseph P. Resavy ,  James R. Stack

IPC分类号： H05K114

CPC分类号： H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/3025 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： Conductive substructures of a multilayered laminate and associated methods of fabrication. The conductive substructures include a 0S1P substructure, a 0S3P substructure, and a 2S1P substructure, in accordance with the notation nSmP, wherein n and m are non-negative integers, wherein S stands for “signal plane,” and wherein P stands for “power plane.” A signal plane is characterized by its inclusion of a layer comprising conductive circuitry. A power plane is characterized by its inclusion of a continuously conductive layer. Thus, a 0S1P substructure includes 0 signal planes and 1 power plane (n=0, m=1). A 0S3P substructure includes 0 signal planes and 3 power plane (n=0, m=3) with a dielectric layer between each pair of power planes. A 2S1P substructure includes 2 signal planes and 1 power plane (n=2, m=1) with a dielectric layer between the power plane and each signal plane. A multilayered laminate includes a stacked substructure configuration having any combination of 0S1P, 0S3P, and 2S1P substructures with dielectric material insulatively separating the substructures from one another.

摘要翻译： 多层层压板的导电子结构和相关的制造方法。 根据符号nSmP，导电子结构包括0S1P子结构，0S3P子结构和2S1P子结构，其中n和m是非负整数，其中S代表“信号面”，其中P代表“功率 飞机“。 信号平面的特征在于其包括包括导电电路的层。 功率平面的特征在于其包括连续导电层。 因此，0S1P子结构包括0个信号平面和1个功率平面（n = 0，m = 1）。 0S3P子结构包括0个信号平面和3个电源平面（n = 0，m = 3），每对电源层之间具有介电层。 2S1P子结构包括2个信号面和1个功率平面（n = 2，m = 1），电源层与每个信号平面之间具有介电层。 多层层压板包括具有0S1P，0S3P和2S1P子结构的任何组合的堆叠的子结构配置，其中介电材料将子结构彼此绝缘地分离。

公开(公告)号：US07255571B2

公开(公告)日：2007-08-14

申请号：US11521158

申请日：2006-09-14

申请人： William L. Brodsky ,  James A. Busby ,  Bruce J. Chamberlin ,  Mitchell G. Ferrill ,  Robin A. Susko ,  James R. Wilcox

发明人： William L. Brodsky ,  James A. Busby ,  Bruce J. Chamberlin ,  Mitchell G. Ferrill ,  Robin A. Susko ,  James R. Wilcox

IPC分类号： H01R12/00

CPC分类号： H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0501 ,  H01L2224/05011 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30107 ,  H01R4/01 ,  H01R12/52 ,  H05K3/325 ,  H05K2201/068 ,  H05K2201/209 ,  H05K2203/1105 ,  H01L2224/05099

摘要： A method and structure is disclosed for forming a removable interconnect for semiconductor packages, where the connector is adapted to repeatedly change from a first shape into a second shape upon being subjected to a temperature change and to repeatedly return to the first shape when not being subjected to the temperature change. The connector can be disconnected when the connector is in its second shape and the connector cannot be disconnected when the connector is in its first shape.

摘要翻译： 公开了一种用于形成用于半导体封装的可移除互连的方法和结构，其中连接器适于在经受温度变化时从第一形状重复地变为第二形状，并且在不受影响时重复地返回到第一形状 到温度变化。 当连接器处于其第二形状时，连接器可以断开，并且当连接器处于其第一形状时连接器不能断开。