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41 条记录 (耗时 0.035 秒)

    Electrically erasable memory elements having improved set resistance stability
    6.
    发明授权
    Electrically erasable memory elements having improved set resistance stability 失效
    具有改进的电阻稳定性的电可擦除存储元件

    公开(公告)号：US5414271A

    公开(公告)日：1995-05-09

    申请号：US789234

    申请日：1991-11-07

    申请人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    发明人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00

    CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1625 ,  G11C13/04 ,  G11C2213/72

    摘要： A solid state, directly overwritable, electronic, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory or control array based upon the novel switching characteristics provided by said unique class of semiconductor materials characterized by a large dynamic range of reversible Fermi level positions. The memory or control elements from which the array is fabricated exhibit orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory elements of the instant invention are in turn characterized, inter alia, by numerous stable and non-volatile detectable configurations of local atomic and/or electrode order, which configurations can be selectively and repeatably accessed by electric input signals of yawing energy level. The memory elements are further characterized by enhanced stability, which stability is achieved through the use of compositional modulation of the semiconductor material from which the memory elements are fabricated.

    摘要翻译： 基于由所述独特类型的半导体材料提供的新颖的开关特性，固态，直接可重写的，电子的，非易失性的，高密度的，低成本的，低能量的，高速的，容易制造的多单元单元存储器或控制阵列 通过可逆的费米能级位置的大动态范围。 制造阵列的存储器或控制元件在显着降低的能量水平下显示出更高的开关速度的数量级。 本发明的新颖的记忆元件又特别包括局部原子和/或电极顺序的许多稳定和非易失性的可检测配置，这些配置可以通过偏转能级的电输入信号来选择性地和重复地访问 。 存储元件的特征还在于增强的稳定性，其通过使用制造存储元件的半导体材料的组成调制来实现稳定性。

    Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
    7.
    发明授权
    Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life 失效
    电可擦除存储元件具有降低的开关电流要求和增加的写入/擦除周期寿命

    公开(公告)号：US5341328A

    公开(公告)日：1994-08-23

    申请号：US898635

    申请日：1992-06-15

    申请人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    发明人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1625 ,  G11C13/04 ,  G11C2213/72

    摘要： Disclosed herein is a solid state, directly overwritable, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, single cell memory element having reduced switching current requirements and increased write/erase cycle life. The structurally modified memory element includes an electrical contact formed of amorphous silicon, either alone or in combination with a layer of amorphous carbon layer. The memory element exhibits orders of magnitude higher switching speeds at remarkably reduced switching energy levels. The novel memory elements of the instant invention are further characterized, inter alia, by at least two stable and non-volatile detectable configurations of local atomic and/or electronic order, which configurations can be selectively and repeatably accessed by electrical input signals of designated energies. The reduced switching current requirements and an increased write/erase cycle life are achieved by structurally modifying the electrical contact with the aforementioned layer of amorphous silicon.

    摘要翻译： 本文公开了具有降低的开关电流要求和增加的写入/擦除循环寿命的固态，直接可重写，非易失性，高密度，低成本，低能量，高速度，容易制造的单电池存储元件。 结构改进的记忆元件包括由非晶硅形成的电接触，单独或与无定形碳层组合。 存储元件在显着降低的开关能量水平下显示出更高的开关速度的数量级。 本发明的新颖的记忆元件尤其通过局部原子和/或电子顺序的至少两个稳定和非易失性可检测配置来进一步表征，这些配置可以通过指定能量的电输入信号被选择性地和重复地访问 。 通过结构上改变与上述非晶硅层的电接触来实现降低的开关电流要求和增加的写入/擦除周期寿命。

    Forming a carbon layer between phase change layers of a phase change memory
    9.
    发明授权
    Forming a carbon layer between phase change layers of a phase change memory 有权
    在相变存储器的相变层之间形成碳层

    公开(公告)号：US07649191B2

    公开(公告)日：2010-01-19

    申请号：US11899862

    申请日：2007-09-07

    申请人： Wolodymyr Czubatyj ,  Sergey Kostylev ,  Tyler A. Lowrey ,  Guy C. Wicker

    发明人： Wolodymyr Czubatyj ,  Sergey Kostylev ,  Tyler A. Lowrey ,  Guy C. Wicker

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1233 ,  H01L27/2427 ,  H01L45/00 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/1293 ,  H01L45/141

    摘要： A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

    摘要翻译： 含碳层可以形成在一对含硫族化物的含相变层的层之间。 当下部硫族化物层允许电流通过时，可以在其中形成细丝。 然后，细丝将含碳层的电加热定位，将相对局部化的区域转化为较低的导电性区域。 该区域然后导致加热和电流流过上相变材料层的定位。 在一些实施例中，可能需要较少的相变材料来改变相位以形成相变存储器，从而减少所得到的相变存储器的电流要求。

    Electrically rewritable non-volatile memory element and method of manufacturing the same
    10.
    发明授权
    Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
    电可重写非易失性存储元件及其制造方法

    公开(公告)号：US07589364B2

    公开(公告)日：2009-09-15

    申请号：US11264129

    申请日：2005-11-02

    申请人： Isamu Asano ,  Natsuki Sato ,  Tyler A. Lowrey ,  Guy C. Wicker ,  Wolodymyr Czubatyj ,  Stephen J. Hudgens

    发明人： Isamu Asano ,  Natsuki Sato ,  Tyler A. Lowrey ,  Guy C. Wicker ,  Wolodymyr Czubatyj ,  Stephen J. Hudgens

    IPC分类号： H01L31/112

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

    摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.

    摘要翻译： 非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12， 第一通孔11，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在底部电极13和 记录层15.根据本发明，埋在第一通孔11a中的底部电极13的直径D1小于第二通孔12a的直径D2，从而降低底部电极的热容量 因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，向底部电极逸出的热量 13降低，导致更高的加热效率。