公开(公告)号：US07015739B2

公开(公告)日：2006-03-21

申请号：US10793001

申请日：2004-03-04

Applicant: Woo-Jin Lee ,  Kyu-Hyoun Kim

Inventor： Woo-Jin Lee ,  Kyu-Hyoun Kim

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

Abstract translation: 提供了数字占空比校正电路，其包括占空比检测器电路，其被配置为分别产生与第一内部时钟信号和第二内部时钟信号相关联的第一和第二控制值。 还提供比较器电路，并且被配置为将第一控制值与第二控制值进行比较并提供比较结果。 计数器电路被配置为响应于比较结果执行加法和/或减法操作以提供数字代码。 数模转换器被配置为响应于数字代码产生第三和第四控制值。 最后，占空比校正器电路被配置为接收第一和第二外部时钟信号以及第一至第四控制值，并产生具有校正占空比的第一和第二内部时钟信号。 通过第一路径接收第一和第二控制值，并且通过不同于第一路径的第二路径接收第三和第四控制值。 还提供了操作占空比校正电路的相关方法。

公开(公告)号：US09106361B2

公开(公告)日：2015-08-11

申请号：US13988837

申请日：2010-11-30

Applicant: Ki-Woon Na ,  Woo-Jin Lee ,  Kwon-Hoon Han ,  Seung-Rog Choi ,  Tae-Hyeong Kim ,  Young-Ouk Noh

Inventor： Ki-Woon Na ,  Woo-Jin Lee ,  Kwon-Hoon Han ,  Seung-Rog Choi ,  Tae-Hyeong Kim ,  Young-Ouk Noh

IPC: H04J14/02 ,  H04B10/50 ,  H04B10/572

CPC classification number: H04J14/02 ,  H04B10/50575 ,  H04B10/506 ,  H04B10/572 ,  H04J14/0228 ,  H04J14/0272 ,  H04J14/0282

Abstract: The present invention relates to a passive wavelength division multiplexing device for automatic wavelength locking and a system thereof including an optical multiplexer, an optical filter, an integrated optical receiver monitor, and a tunable optical transmitter. Through wavelength locking that adjusts a wavelength of an optical signal, which changes according to an external environment such as a temperature change, into a wavelength of an optical signal having the maximum optical intensity, communication quality may be maximized by securing a stable communication channel, a locking time and a communication channel setting time may be reduced, and more robust locking may be guaranteed.

Abstract translation: 本发明涉及一种用于自动波长锁定的被动波分复用装置及其系统，包括光复用器，滤光器，集成光接收器监视器和可调光发射器。 通过波长锁定，其将根据诸如温度变化的外部环境变化的光信号的波长调整为具有最大光强度的光信号的波长，通过确保稳定的通信信道可以使通信质量最大化， 可以减少锁定时间和通信信道设置时间，并且可以保证更加鲁棒的锁定。

公开(公告)号：US20120058282A1

公开(公告)日：2012-03-08

申请号：US12875889

申请日：2010-09-03

Applicant: Kuo-wei Hong ,  Akira Shimizu ,  Kunitoshi Namba ,  Woo-Jin Lee

Inventor： Kuo-wei Hong ,  Akira Shimizu ,  Kunitoshi Namba ,  Woo-Jin Lee

IPC: C23C16/505 ,  C23C16/34

CPC classification number: C23C16/45523 ,  C23C16/045 ,  C23C16/345 ,  C23C16/36 ,  C23C16/5096 ,  C23C16/515 ,  H01L21/02167 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a substrate having a patterned surface includes: introducing a reactant gas into a reaction space; introducing a silicon precursor in pulses of less than 5-second duration into the reaction space; applying a first RF power to the reaction space during the pulse of the silicon precursor; applying a second RF power to the reaction space during the interval of the silicon precursor pulse, wherein an average intensity of the second RF power during the interval of the silicon precursor pulse is greater than that of the first RF power during the pulse of the silicon precursor; and repeating the cycle to form a conformal dielectric film having Si—N bonds with a desired thickness on the patterned surface of the substrate.

Abstract translation: 在具有图案化表面的基板上形成具有Si-N键的保形电介质膜的方法包括：将反应气体引入反应空间; 将具有小于5秒持续时间脉冲的硅前体引入反应空间中; 在硅前驱体的脉冲期间将第一RF功率施加到反应空间; 在所述硅前体脉冲的间隔期间将第二RF功率施加到所述反应空间，其中在硅前体脉冲的间隔期间的所述第二RF功率的平均强度大于所述硅脉冲期间的所述第一RF功率的平均强度 前体 并重复该循环以在衬底的图案化表面上形成具有期望厚度的具有Si-N键的保形电介质膜。

公开(公告)号：US08095180B2

公开(公告)日：2012-01-10

申请号：US12422924

申请日：2009-04-13

Applicant: Woo-Jin Lee ,  Kyoung-Taek Lim ,  Byung-Duck Park ,  Sang-Chul Jeon

Inventor： Woo-Jin Lee ,  Kyoung-Taek Lim ,  Byung-Duck Park ,  Sang-Chul Jeon

IPC: H04M1/00

CPC classification number: H04M1/22 ,  H04M1/0237 ,  H04M2250/22 ,  H04M2250/52

Abstract: A mobile terminal includes a housing comprising a light emitting portion disposed on at least a portion of the housing, a light emitting unit disposed inside the housing, a light transmission member configured to transmit light emitted from the light emitting unit, and a guiding structure formed on the light transmission member and configured to direct and emit the light toward the light emitting portion.

Abstract translation: 移动终端包括壳体，其包括设置在壳体的至少一部分上的发光部分，设置在壳体内部的发光单元，被配置为透射从发光单元发射的光的光传输部件和形成的引导结构 在所述光传输部件上并且被配置为朝向所述发光部分引导和发射所述光。

公开(公告)号：US07919416B2

公开(公告)日：2011-04-05

申请号：US12357174

申请日：2009-01-21

Applicant: Woo-Jin Lee ,  Akira Shimizu ,  Atsuki Fukazawa

Inventor： Woo-Jin Lee ,  Akira Shimizu ,  Atsuki Fukazawa

IPC: H01L21/337

CPC classification number: C23C16/345 ,  C23C16/045 ,  C23C16/45523 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3185

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Abstract translation: 通过等离子体增强化学气相沉积（PECVD）在半导体衬底上形成具有Si-N键的共形电介质膜的方法包括：将含氮和氢的反应气体和添加气体引入反应空间内， 底物放置; 向反应空间施加RF功率; 并将含氢的硅前体以脉冲方式引入到等离子体被激发的反应空间中，从而在衬底上形成具有Si-N键的保形电介质膜。

公开(公告)号：US07751851B2

公开(公告)日：2010-07-06

申请号：US10287197

申请日：2002-11-04

Applicant: Woo-Jin Lee ,  Yong-Nam Kim

Inventor： Woo-Jin Lee ,  Yong-Nam Kim

IPC: H04M1/00

CPC classification number: H04M1/72566 ,  H04M1/274575

Abstract: A method for managing a schedule as a supplementary function of a mobile communication terminal. The method is capable of efficiently managing schedule information such as anniversaries to be repeated every year. Further, the method is capable of conveniently making contact with another party by providing telephone numbers of the other party at the same time when the schedule information is provided to a user.

Abstract translation: 一种用于管理时间表作为移动通信终端的补充功能的方法。 该方法能够有效地管理每年要重复的周年纪念日程信息。 此外，该方法能够通过在将调度信息提供给用户的同时提供对方的电话号码来方便地与另一方进行联系。

公开(公告)号：US20080056018A1

公开(公告)日：2008-03-06

申请号：US11896722

申请日：2007-09-05

Applicant: Joung-Yeal Kim ,  Jeong-Don Lim ,  Sung-Hoon Kim ,  Woo-Jin Lee

Inventor： Joung-Yeal Kim ,  Jeong-Don Lim ,  Sung-Hoon Kim ,  Woo-Jin Lee

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C2207/107

Abstract: According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.

Abstract translation: 根据示例实施例，半导体存储器件可以包括存储器芯，输入电路和/或输出电路。 输入电路可以被配置为使用响应于在不同周期期间启用的输入控制信号而工作的锁存电路从第一数据产生第二数据。 输入电路还可以被配置为向存储器核提供第二数据。 第二数据可以具有2N次第一数据的比特数，其中N是正整数。 输出电路可以被配置为使用响应于在不同周期期间启用的输出控制信号而工作的锁存电路从第三数据生成第四数据。 输出电路还可以被配置为向数据输出引脚提供第四数据。 第四数据可以具有第三数据的比特数的1/2N倍。 还提供了一种输入/输出数据的方法。

公开(公告)号：US20060255829A1

公开(公告)日：2006-11-16

申请号：US11429296

申请日：2006-05-05

Applicant: Hyun-Jin Kim ,  Kwang-Il Park ,  Woo-Jin Lee

Inventor： Hyun-Jin Kim ,  Kwang-Il Park ,  Woo-Jin Lee

IPC: H03K17/16

CPC classification number: G06F13/4072 ,  H04L25/0278 ,  H04L25/028

Abstract: A semiconductor memory device includes a primary output driver which outputs a data signal through an output terminal; a secondary output driver which is connected to the output terminal and performs a pre-emphasis operation; and a pre-emphasis signal generator which outputs a pre-emphasis signal to enable the secondary output driver The pre-emphasis signal generator includes a auto pulse generator which generates an auto pulse in response to a transition of a control signal; a delay circuit which receives the auto pulse output from the auto pulse generator, delays the auto pulse by a predetermined period, and outputs a pre-emphasis signal; and a delay control unit which applies a delay control signal to the delay circuit and controls a delay amount of the delay circuit.

Abstract translation: 半导体存储器件包括通过输出端输出数据信号的初级输出驱动器; 二次输出驱动器，其连接到输出端子并执行预加重操作; 以及预加重信号发生器，其输出预加重信号以使得辅助输出驱动器。预加重信号发生器包括自动脉冲发生器，其响应于控制信号的转变而产生自动脉冲; 接收从自动脉冲发生器输出的自动脉冲的延迟电路将自动脉冲延迟预定周期，并输出预加重信号; 以及延迟控制单元，其向延迟电路施加延迟控制信号并控制延迟电路的延迟量。

公开(公告)号：US20160163589A1

公开(公告)日：2016-06-09

申请号：US14955988

申请日：2015-12-01

Applicant: Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

Inventor： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047

Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Abstract translation: 形成半导体器件的方法可以包括使用具有选择为提供对后续蚀刻工艺的电阻的组成的材料形成绝缘层。 可以改变材料的组成以将材料的电阻降低到绝缘层中预定水平的后续蚀刻工艺。 可以在绝缘层上执行随后的蚀刻工艺，以将绝缘层的上部去除在预定水平以上，并且将绝缘层的下部分留在延伸穿过绝缘层的下部的相邻导电图案之间的预定水平以下 。 可以在相邻导电图案之间的绝缘层的下部上形成低k介电材料，以将绝缘层的上部替换为高于预定水平。

公开(公告)号：US20160079115A1

公开(公告)日：2016-03-17

申请号：US14703556

申请日：2015-05-04

Applicant: Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

Inventor： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76843 ,  H01L2221/1063

Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Abstract translation: 一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成 包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案， 衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。