Phase change memory devices employing cell diodes and methods of fabricating the same
    2.
    发明申请
    Phase change memory devices employing cell diodes and methods of fabricating the same 有权
    使用单元二极管的相变存储器件及其制造方法

    公开(公告)号:US20060186483A1

    公开(公告)日:2006-08-24

    申请号:US11324112

    申请日:2005-12-30

    IPC分类号: H01L29/76

    摘要: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

    摘要翻译: 提供具有单元二极管和相关方法的相变存储器件,其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线,字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面,沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案,第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上,在具有第二半导体图案的基板上设置绝缘层,绝缘层填充字线之间的间隙区域,第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上,并且相变材料图案分别电连接到第二半导体图案。

    PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME 有权
    使用单元的相变存储器件及其制造方法

    公开(公告)号:US20080303016A1

    公开(公告)日:2008-12-11

    申请号:US12196137

    申请日:2008-08-21

    IPC分类号: H01L45/00

    摘要: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

    摘要翻译: 提供具有单元二极管和相关方法的相变存储器件,其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线,字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面,沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案,第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上,在具有第二半导体图案的基板上设置绝缘层,绝缘层填充字线之间的间隙区域,第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上,并且相变材料图案分别电连接到第二半导体图案。

    Phase change memory devices employing cell diodes and methods of fabricating the same
    4.
    发明授权
    Phase change memory devices employing cell diodes and methods of fabricating the same 有权
    使用单元二极管的相变存储器件及其制造方法

    公开(公告)号:US07427531B2

    公开(公告)日:2008-09-23

    申请号:US11324112

    申请日:2005-12-30

    IPC分类号: H01L21/06

    摘要: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

    摘要翻译: 提供具有单元二极管和相关方法的相变存储器件,其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线,字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面,沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案,第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上,在具有第二半导体图案的基板上设置绝缘层,绝缘层填充字线之间的间隙区域,第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上,并且相变材料图案分别电连接到第二半导体图案。

    Memory cell array biasing method and a semiconductor memory device
    5.
    发明授权
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号:US07317655B2

    公开(公告)日:2008-01-08

    申请号:US11327967

    申请日:2006-01-09

    IPC分类号: G11C8/00

    摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

    摘要翻译: 提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。 半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到多条第一线路中的相应第一线路,而存储器单元的第二端子连接到 多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

    Memory cell array biasing method and a semiconductor memory device
    6.
    发明申请
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号:US20060164896A1

    公开(公告)日:2006-07-27

    申请号:US11327967

    申请日:2006-01-09

    IPC分类号: G11C7/00

    摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

    摘要翻译: 提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。 半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到多条第一线路中的相应第一线路,而存储器单元的第二端子连接到 多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

    Memory cell array biasing method and a semiconductor memory device
    7.
    发明授权
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号:US07710767B2

    公开(公告)日:2010-05-04

    申请号:US11969326

    申请日:2008-01-04

    IPC分类号: G11C11/00

    摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

    摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

    Memory cell array biasing method and a semiconductor memory device
    8.
    发明授权
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号:US08248842B2

    公开(公告)日:2012-08-21

    申请号:US12732990

    申请日:2010-03-26

    IPC分类号: G11C11/00

    摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

    摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路,用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。

    MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE 有权
    存储单元阵列偏移方法和半导体存储器件

    公开(公告)号:US20100246248A1

    公开(公告)日:2010-09-30

    申请号:US12732990

    申请日:2010-03-26

    IPC分类号: G11C11/00 G11C8/08

    摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

    摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路,用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。