公开(公告)号：US07794799B1

公开(公告)日：2010-09-14

申请号：US10438334

申请日：2003-05-15

申请人： Woon-bae Kim ,  Chang-ho Cho ,  Kae-dong Back ,  Hwan-young Choi

发明人： Woon-bae Kim ,  Chang-ho Cho ,  Kae-dong Back ,  Hwan-young Choi

IPC分类号： B05D3/00

CPC分类号： B82Y30/00 ,  B01J19/0046 ,  B01J2219/00274 ,  B01J2219/00432 ,  B01J2219/00585 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/0061 ,  B01J2219/00612 ,  B01J2219/00619 ,  B01J2219/00626 ,  B01J2219/00637 ,  B01J2219/00659 ,  B01J2219/00722 ,  B01J2219/00725 ,  B01J2219/00731 ,  B01L3/5088 ,  B01L2200/12 ,  C07B2200/11 ,  C40B40/06 ,  C40B40/10 ,  C40B40/12 ,  C40B60/14

摘要： A method for manufacturing an array plate for biomolecules includes coating a surface of a substrate with a hydrophobic material to form a hydrophobic layer having initial hydrophobic properties, etching the hydrophobic layer through an etch mask placed thereon to form a hydrophilic binding site, removing the etch mask, and processing the remaining region of the hydrophobic layer to recover the initial hydrophobic properties. A method for manufacturing a biochip using this array plate, includes processing the surface of the hydrophilic binding site of the array plate to increase an affinity of biomolecules to the hydrophilic binding site, and applying a solution containing biomolecules to the surface of the hydrophilic binding site.

摘要翻译： 用于制造生物分子阵列板的方法包括用疏水材料涂覆基材的表面以形成具有初始疏水性质的疏水层，通过其上放置的蚀刻掩模蚀刻疏水层以形成亲水性结合位点，除去蚀刻 掩模，并处理疏水层的剩余区域以恢复初始疏水性质。 使用该阵列板制造生物芯片的方法包括加工阵列板的亲水性结合位点的表面以增加生物分子对亲水结合位点的亲和力，并将含有生物分子的溶液施加到亲水结合位点的表面 。

公开(公告)号：US20070013058A1

公开(公告)日：2007-01-18

申请号：US11481012

申请日：2006-07-06

申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

公开(公告)号：US07579685B2

公开(公告)日：2009-08-25

申请号：US11339500

申请日：2006-01-26

申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

IPC分类号： H01L23/12 ,  H01L23/043

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

摘要翻译： 提供了一种用于晶片级封装的晶片级封装盖及其方法。 覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线 盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和 填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫 并且电连接到多个连接杆。

公开(公告)号：US07786573B2

公开(公告)日：2010-08-31

申请号：US11481012

申请日：2006-07-06

申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

IPC分类号： H01L23/34 ,  H01R12/16 ,  H05K1/11

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

公开(公告)号：US20060175707A1

公开(公告)日：2006-08-10

申请号：US11339500

申请日：2006-01-26

申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

IPC分类号： H01L23/52

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

公开(公告)号：US06906845B2

公开(公告)日：2005-06-14

申请号：US10690537

申请日：2003-10-23

申请人： Chang-ho Cho ,  Hyung-jae Shin ,  Woon-bae Kim

发明人： Chang-ho Cho ,  Hyung-jae Shin ,  Woon-bae Kim

IPC分类号： B81B3/00 ,  B81C1/00 ,  G02B26/08 ,  G02B26/00

CPC分类号： G02B26/0841 ,  B81B3/0005 ,  B81B2201/042 ,  B81C1/0096 ,  B81C2201/112

摘要： The micro-mechanical structure includes an anti-stiction layer formed by plasma enhanced chemical vapor deposition and plasma etching. The anti-stiction layer is selectively formed on only the area of a substrate other than the top of a movable structure and a part of an electrode that is subsequently bonded to a wire.

摘要翻译： 微机械结构包括通过等离子体增强化学气相沉积和等离子体蚀刻形成的抗静电层。 抗静电层仅选择性地形成在除了可移动结构的顶部之外的基底的区域和随后结合到线的电极的一部分上。

公开(公告)号：US20050161757A1

公开(公告)日：2005-07-28

申请号：US11087552

申请日：2005-03-24

申请人： Chang-ho Cho ,  Hyung-Jae Shin ,  Woon-bae Kim

发明人： Chang-ho Cho ,  Hyung-Jae Shin ,  Woon-bae Kim

IPC分类号： H01L23/14 ,  B81B7/00 ,  B81C1/00 ,  H01L21/50 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L21/44

CPC分类号： H01L23/10 ,  B81B7/0077 ,  B81C1/00269 ,  B81C1/00357 ,  B81C2201/019 ,  H01L21/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device that is hermetically sealed at a wafer level or a method of hermetically sealing a device, which is sensitive to high temperatures or affected by heating cycles. Semiconductor devices are formed on a wafer. A lid wafer is formed. Adhesives are formed in a predetermined position over the wafer and/or the lid wafer. The wafer and the lid wafer are sealed by the adhesives at the wafer level. The sealing may be performed at a low temperature using a solder to protect the devices sensitive to heat. The sealed devices are diced into individual chips. In the wafer level hermetic sealing method, a sawing operation is performed after the devices are sealed. Therefore, the overall processing time is reduced, devices are protected from the effects of moisture or particles, and devices having a moving structure, such as MEMS devices, are more easily handled.

公开(公告)号：US07065867B2

公开(公告)日：2006-06-27

申请号：US10293933

申请日：2002-11-14

申请人： Woon-bae Kim ,  Hyung-jae Shin ,  Chang-ho Cho ,  Seung-goo Kang

发明人： Woon-bae Kim ,  Hyung-jae Shin ,  Chang-ho Cho ,  Seung-goo Kang

IPC分类号： H05K3/30

CPC分类号： B81C1/00269 ,  H01L21/50 ,  H01L23/10 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/163 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49789 ,  Y10T29/49794 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A hermetic sealing method, which is capable of preventing oxidation of a micro-electromechanical system (MEMS) and sealing the MEMS at a low temperature. A low temperature hermetic sealing method having a passivation layer includes depositing a junction layer, a wetting layer, and a solder layer on a prepared lid frame, depositing a first protection layer for preventing oxidation on the solder layer and forming a lid, preparing a package base on which a device is disposed, and in which a metal layer and a second protection layer are formed around the device, and assembling the lid and the package base, heating, and sealing them. The protection layer is laminated on the solder layer that is formed by the lid, thereby preventing oxidation without using a flux. The low temperature hermetic sealing method having a passivation layer is suitable for sealing a device, such as the MEMS, which is sensitive to heat, water and other by-products.

公开(公告)号：US06969639B2

公开(公告)日：2005-11-29

申请号：US09984734

申请日：2001-10-31

申请人： Chang-ho Cho ,  Hyung-jae Shin ,  Woon-bae Kim

发明人： Chang-ho Cho ,  Hyung-jae Shin ,  Woon-bae Kim

IPC分类号： H01L23/14 ,  B81B7/00 ,  B81C1/00 ,  H01L21/50 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L23/10 ,  B81B7/0077 ,  B81C1/00269 ,  B81C1/00357 ,  B81C2201/019 ,  H01L21/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device that is hermetically sealed at a wafer level or a method of hermetically sealing a device, which is sensitive to high temperatures or affected by heating cycles. Semiconductor devices are formed on a wafer. A lid wafer is formed. Adhesives are formed in a predetermined position over the wafer and/or the lid wafer. The wafer and the lid wafer are sealed by the adhesives at the wafer level. The sealing may be performed at a low temperature using a solder to protect the devices sensitive to heat. The sealed devices are diced into individual chips. In the wafer level hermetic sealing method, a sawing operation is performed after the devices are sealed. Therefore, the overall processing time is reduced, devices are protected from the effects of moisture or particles, and devices having a moving structure, such as MEMS devices, are more easily handled.

摘要翻译： 在晶片级气密密封的装置或密封装置的方法，其对高温敏感或受加热循环影响。 半导体器件形成在晶片上。 形成盖子晶片。 粘合剂形成在晶片和/或盖晶片上的预定位置。 晶片和盖晶片在晶片级被粘合剂密封。 可以使用焊料在低温下进行密封以保护对热敏感的装置。 将密封的装置切成单独的芯片。 在晶片级密封方法中，在密封装置之后进行锯切操作。 因此，总体处理时间减少，防止装置受潮湿或微粒的影响，并且具有诸如MEMS装置的移动结构的装置更容易处理。

公开(公告)号：US09164278B2

公开(公告)日：2015-10-20

申请号：US13461387

申请日：2012-05-01

申请人： Dong-sik Shim ,  Jong-seok Kim ,  Yong-seop Yoon ,  Hyung Choi ,  Woon-bae Kim

发明人： Dong-sik Shim ,  Jong-seok Kim ,  Yong-seop Yoon ,  Hyung Choi ,  Woon-bae Kim

IPC分类号： G02B26/02 ,  G02B26/08

CPC分类号： G02B26/0841

摘要： A micro-optical switching device, an image display apparatus including the micro-optical switching device, and a method of manufacturing the micro-optical switching device are provided. The micro-optical switching device includes a substrate; a first electrode disposed on the substrate and including a first opening array, wherein the first opening array includes a plurality of openings; and a second electrode disposed spaced apart from the first electrode and including a second opening array including a plurality of openings, wherein the plurality of openings of the second opening array do not overlap with the plurality of openings of the first opening array.

摘要翻译： 提供一种微型光开关装置，包括该微型光开关装置的图像显示装置以及该微型光开关装置的制造方法。 微光开关装置包括：基板; 第一电极，其设置在所述基板上并且包括第一开口阵列，其中所述第一开口阵列包括多个开口; 以及第二电极，与第一电极间隔开并且包括包括多个开口的第二开口阵列，其中第二开口阵列的多个开口不与第一开口阵列的多个开口重叠。