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公开(公告)号：US20220075522A1
公开(公告)日：2022-03-10
申请号：US17231133
申请日：2021-04-15
IPC分类号： G06F3/06
摘要： A virtual memory management method applied to an intelligent processor including an operation accelerator includes: determining m storage units from a physical memory, the m storage units forming a virtual memory; dividing the m storage units into n storage groups; determining an address mapping relationship for each storage group to obtain n address mapping relationships, the n address mapping relationship being correspondence of between n virtual addresses of the virtual memory and physical addresses of the m storage units, where m and n are dynamically updated according to requirements of the operation accelerator. In the method, the number of the storage units in each storage group can be configured according to requirements of the operation accelerator, and a data storage bit width and a data storage depth of the virtual memory are dynamically updated to thereby improve data access efficiency.
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2.发明申请公开(公告)号：US20220036167A1
公开(公告)日：2022-02-03
申请号：US17335569
申请日：2021-06-01
摘要： An operation method in a convolutional neural network applied to an electronic apparatus having a memory storing convolutional kernel data having undergone a sorting process. The operation method includes: performing the sorting process on a first feature vector of feature map data under process according to a marking sequence corresponding to a first weighting vector of the convolutional kernel data having undergone the sorting process; removing a part of feature values in the first feature vector having undergone the sorting process to generate a second feature vector; and performing a multiply accumulation operation on the basis of the first weighting vector and the second feature vector. The convolutional kernel data having undergone the sorting process is obtained by means of performing sorting and zero-weighting removal processes, and the marking sequence is generated according to the sorting and zero-weighting removal processes corresponding to the first weighting vector.
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公开(公告)号：US20210349692A1
公开(公告)日：2021-11-11
申请号：US17146946
申请日：2021-01-12
摘要： A multiplier includes a multiplier preprocessing circuit, an encoding code, an addition circuit and a partial product selection circuit. The multiplier preprocessing circuit generates different input coding values from a received multiplier according to different operation bit widths. The encoding circuit generates different coded values according to different input coding values, and performs an operation according to different coded values and a received multiplicand to obtain a first partial product. The addition circuit accumulates the first partial product for a corresponding number of times according to different operation bit widths to generate different second partial products. The multiplier supports multiplication of multiple mixed bit widths, and a multiplier unit can be repeatedly used for multiplication operations in encounters with different precisions.
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公开(公告)号：US20210224033A1
公开(公告)日：2021-07-22
申请号：US17134660
申请日：2020-12-28
发明人： Xiaofeng LI , Chengwei ZHENG , Bo LIN
摘要： An operation device includes a quantizer circuit, a buffer circuit, a convolution core circuit and a multiply-add circuit. The quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data. The quantizer circuit further receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weight coefficient. The convolution core circuit performs a convolution operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result.
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公开(公告)号：US20220036162A1
公开(公告)日：2022-02-03
申请号：US17159217
申请日：2021-01-27
发明人： Tao XU , Chengwei ZHENG , Xiaofeng LI , Bo LIN
摘要： A network model quantization method includes: acquiring a target floating-point network model that is to be model quantized; determining an asymmetric quantization interval corresponding to an input value of the target floating-point network model; determining a symmetric quantization interval corresponding to a weight value of the target floating-point network model; and performing fixed-point quantization on the input value of the target floating-point network model according to the asymmetric quantization interval, and performing the fixed-point quantization on the weight value of the target floating-point network model according to the symmetric quantization interval to obtain a fixed-point network model corresponding to the target floating-point network model.
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公开(公告)号：US20210157594A1
公开(公告)日：2021-05-27
申请号：US17103036
申请日：2020-11-24
摘要： A data temporary storage apparatus includes a moving unit coupled to a first storage unit and multiple second storage units. The moving unit receives a moving instruction having contents including a read address, a destination address and a predetermined moving rule. The moving unit further executes the moving instruction to fetch input data by row from the first storage unit according to the read address, and to temporarily stores one after another in an alternate and sequential manner the data in each row to each of the second storage units indicated by the destination address. The data moving, data reading and convolution approaches of the present invention implement in parallel data moving and a convolution operation, achieving a ping-pong operation of convolution units and enhancing convolution efficiency, while reducing memory costs since configuring two data storage spaces in a memory is not necessary.
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