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    SYSTEMS AND METHODS FOR HARDWARE MESSAGE PROCESSING
    1.
    发明申请
    SYSTEMS AND METHODS FOR HARDWARE MESSAGE PROCESSING 有权

    公开(公告)号：US20250112933A1

    公开(公告)日：2025-04-03

    申请号：US18478438

    申请日：2023-09-29

    Applicant: Xilinx, Inc.

    Inventor： David Andrews ,  David Lawrie ,  Victor Wu ,  Po-Ching Sun ,  Dmitri Kitariev ,  David Riddoch

    IPC: H04L9/40 ,  H04L1/00 ,  H04L43/0823

    Abstract: Described herein are systems and methods for managing error detection in a message. A circuit can identify, based on an error detection configuration of the at least one circuit, a first portion of the message to be checked for errors before a second portion of the message is available to the at least one circuit, the first portion being less than all of the message to be checked for one or more errors. A circuit can analyze a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration. A circuit can, based on analyzing the first portion, determine whether the message includes the one or more errors. Various other methods, systems, and computer-readable media are also disclosed.

    SYSTEMS AND METHODS FOR MANAGING ORDER OF COMMAND PROCESSING
    2.
    发明申请
    SYSTEMS AND METHODS FOR MANAGING ORDER OF COMMAND PROCESSING 有权

    公开(公告)号：US20250004782A1

    公开(公告)日：2025-01-02

    申请号：US18345994

    申请日：2023-06-30

    Applicant: Xilinx, Inc.

    Inventor： Mark Richard Nethercot ,  Martin Rhodes ,  Ricardo Gonzalez Toral ,  Colin Stirling ,  Dmitri Kitariev ,  David Riddoch

    IPC: G06F9/38

    Abstract: A computer-implemented method for managing processing order for a plurality of commands can include in response to receiving each command of a plurality of commands in a receipt order, assigning each respective command of the plurality of commands to a respective processing queue of a plurality of processing queues to be processed, and setting, for each of the plurality of commands and in the receipt order, an identifier based on the respective queue assigned to each of the plurality of commands, and managing, based on the identifiers for each of the plurality of commands in the receipt order, an order of processing of each of the plurality of commands from the respective processing queue of the plurality of processing queues. Various other methods, systems, and computer-readable media are also disclosed.

    Network interface device
    4.
    发明授权
    Network interface device 有权

    公开(公告)号：US11824830B2

    公开(公告)日：2023-11-21

    申请号：US17246310

    申请日：2021-04-30

    Applicant: Xilinx, Inc.

    Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

    IPC: H04L29/06 ,  H04L9/40

    CPC classification number: H04L63/0227 ,  H04L63/029

    Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

    Programmed input/output mode
    6.
    发明授权
    Programmed input/output mode 有权

    公开(公告)号：US11023411B2

    公开(公告)日：2021-06-01

    申请号：US16541070

    申请日：2019-08-14

    Applicant: XILINX, INC.

    Inventor： Steven L. Pope ,  David J. Riddoch ,  Dmitri Kitariev

    IPC: H04L12/26 ,  G06F15/173 ,  G06F13/38 ,  G06F3/06 ,  G06F13/28 ,  H04L29/08 ,  G06F9/455 ,  H04L12/861

    Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.

    Network Interface Device
    7.
    发明申请
    Network Interface Device 审中-公开

    公开(公告)号：US20200274827A1

    公开(公告)日：2020-08-27

    申请号：US16870814

    申请日：2020-05-08

    Applicant: Xilinx, Inc.

    Inventor： Steven L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Dmitri Kitariev

    IPC: H04L12/931 ,  H04L12/883 ,  H04L12/935 ,  H04L29/06 ,  H04L12/933 ,  H04L12/721

    Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.

    Network interface device
    8.
    发明授权
    Network interface device 有权

    公开(公告)号：US10686731B2

    公开(公告)日：2020-06-16

    申请号：US16226453

    申请日：2018-12-19

    Applicant: XILINX, INC.

    Inventor： Steven L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Dmitri Kitariev

    IPC: H04L12/931 ,  H04L12/883 ,  H04L12/935 ,  H04L29/06 ,  H04L12/933 ,  H04L12/721

    Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.

    Network interface device
    9.
    发明授权
    Network interface device 有权

    公开(公告)号：US12224954B2

    公开(公告)日：2025-02-11

    申请号：US17515343

    申请日：2021-10-29

    Applicant: Xilinx, Inc.

    Inventor： Steven L. Pope ,  Dmitri Kitariev ,  Derek Roberts

    IPC: G06N20/00 ,  G06F9/50 ,  H04L9/40 ,  H04L45/00 ,  H04L47/34 ,  H04L49/90

    Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.

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