公开(公告)号：US07548029B2

公开(公告)日：2009-06-16

申请号：US11144205

申请日：2005-06-02

申请人： Xiao-Chang Cheng ,  Jun Honda ,  Dana Wilhelm

发明人： Xiao-Chang Cheng ,  Jun Honda ,  Dana Wilhelm

IPC分类号： G05F1/00

CPC分类号： G01R17/10 ,  G01R19/0092 ,  G01R31/40 ,  H02M2001/0009

摘要： An apparatus and method for determining the output current in a bridge-connected switched transistor output circuit including high-side and low-side transistor switches, typically MOSFETS. The voltage at a common node between the high and low side switches is sensed, and offset in a first circuit by a fixed amount so that the voltage is positive for all positive or negative output currents of interest. The output current is actually determined in a second circuit which receives the offset voltage signal only predetermined times in relation to the on-time of the low side switch. The first circuit includes a current reference source/level shifter and a current mirror circuit formed of a plurality of transistors in a particular circuit configuration. The second circuit is coupled to an output of the first circuit by a gated NMOS transistor at the desired times to provide the current measurement signal. The second circuit includes a second current reference source having substantially the same electrical characteristics as the first current reference source, and a second plurality of transistors respectively matched to the input side circuit transistors, and connected in the same circuit configuration. In the second circuit, the offset signal is compared with high and low reference signals to provide an indication if the output current exceeds an overcurrent limit, either positively or negatively. The sensing circuit is advantageously integrated with the output circuit gate driver in a single IC.

摘要翻译： 一种用于确定桥接开关晶体管输出电路中的输出电流的装置和方法，该电路包括高侧和低侧晶体管开关，典型地是MOSFET。 感测高侧和低侧开关之间的公共节点处的电压，并且在第一电路中偏移固定的量，使得所有感兴趣的正或负输出电流的电压为正。 输出电流实际上是在相对于低侧开关的导通时间仅接收到预定时间的偏移电压信号的第二电路中确定的。 第一电路包括电流参考源/电平移位器和由特定电路配置中的多个晶体管形成的电流镜电路。 第二电路在期望的时间通过门控NMOS晶体管耦合到第一电路的输出，以提供电流测量信号。 第二电路包括具有与第一电流参考源基本相同的电特性的第二电流参考源和分别与输入侧电路晶体管匹配并以相同电路配置连接的第二多个晶体管。 在第二电路中，将偏移信号与高和低参考信号进行比较，以提供输出电流是否超过过电流极限的指示，无论是正极还是负极。 感测电路有利地与单个IC中的输出电路栅极驱动器集成。

公开(公告)号：US20050270012A1

公开(公告)日：2005-12-08

申请号：US11144205

申请日：2005-06-02

申请人： Xiao-Chang Cheng ,  Jun Honda ,  Dana Wilhelm

发明人： Xiao-Chang Cheng ,  Jun Honda ,  Dana Wilhelm

IPC分类号： G01R17/10 ,  G01R19/00 ,  G01R31/28 ,  G01R31/40

CPC分类号： G01R17/10 ,  G01R19/0092 ,  G01R31/40 ,  H02M2001/0009

摘要： An apparatus and method for determining the output current in a bridge-connected switched transistor output circuit including high-side and low-side transistor switches, typically MOSFETS. The voltage at a common node between the high and low side switches is sensed, and offset in a first circuit by a fixed amount so that the voltage is positive for all positive or negative output currents of interest. The output current is actually determined in a second circuit which receives the offset voltage signal only predetermined times in relation to the on-time of the low side switch. The first circuit includes a current reference source/level shifter and a current mirror circuit formed of a plurality of transistors in a particular circuit configuration. The second circuit is coupled to an output of the first circuit by a gated NMOS transistor at the desired times to provide the current measurement signal. The second circuit includes a second current reference source having substantially the same electrical characteristics as the first current reference source, and a second plurality of transistors respectively matched to the input side circuit transistors, and connected in the same circuit configuration. In the second circuit, the offset signal is compared with high and low reference signals to provide an indication if the output current exceeds an overcurrent limit, either positively or negatively. The sensing circuit is advantageously integrated with the output circuit gate driver in a single IC.

摘要翻译： 一种用于确定桥接开关晶体管输出电路中的输出电流的装置和方法，该电路包括高侧和低侧晶体管开关，典型地是MOSFET。 感测高侧和低侧开关之间的公共节点处的电压，并且在第一电路中偏移固定的量，使得所有感兴趣的正或负输出电流的电压为正。 输出电流实际上是在相对于低侧开关的导通时间仅接收到预定时间的偏移电压信号的第二电路中确定的。 第一电路包括电流参考源/电平移位器和由特定电路配置中的多个晶体管形成的电流镜电路。 第二电路在期望的时间通过门控NMOS晶体管耦合到第一电路的输出，以提供电流测量信号。 第二电路包括具有与第一电流参考源基本相同的电特性的第二电流参考源和分别与输入侧电路晶体管匹配并以相同电路配置连接的第二多个晶体管。 在第二电路中，将偏移信号与高和低参考信号进行比较，以提供输出电流是否超过过电流极限的指示，无论是正极还是负极。 感测电路有利地与单个IC中的输出电路栅极驱动器集成。

公开(公告)号：US20070247774A1

公开(公告)日：2007-10-25

申请号：US11736679

申请日：2007-04-18

申请人： Xiao-chang Cheng ,  Jun Honda ,  Gabriele Bernardinis

发明人： Xiao-chang Cheng ,  Jun Honda ,  Gabriele Bernardinis

IPC分类号： H02H3/08

CPC分类号： H02H1/04

摘要： A circuit for providing over-current protection, the circuit including a gate driver circuit for controlling a bridge circuit including a half bridge stage having high and low switches. The circuit includes a feedback loop circuit for counting over-current indicators sensed during one or more consecutive PWM cycles; wherein when an over-current indicator is sensed, the low switch is turned OFF for duration of a first time period after which the low switch is turned back ON, to enable determination of an over-current condition where false noise signals are rejected thereby preventing circuit shutdowns due to false over-current condition.

摘要翻译： 一种用于提供过电流保护的电路，所述电路包括用于控制包括具有高和低开关的半桥级的桥式电路的栅极驱动电路。 电路包括用于对在一个或多个连续PWM周期期间感测到的过电流指示进行计数的反馈回路电路; 其中，当检测到过电流指示器时，低电平开关在第一时间段的持续时间内被关闭，在此之后低开关被重新接通，以便能够确定错误噪声信号被拒绝的过电流状态，从而防止 由于过电流故障导致电路关断。

公开(公告)号：US20060054938A1

公开(公告)日：2006-03-16

申请号：US11221240

申请日：2005-09-06

申请人： Jun Honda ,  Xiao-Chang Cheng

发明人： Jun Honda ,  Xiao-Chang Cheng

IPC分类号： H01L27/148

CPC分类号： H03K17/08122 ,  H03K5/1515 ,  H03K19/0013

摘要： A dead-time generator for incorporation in an integrated circuit wherein the integrated circuit includes a high side and low side gate driver and wherein the high side and low side gate driver drive output switches such that a dead-time is provided between on times of the output switches, the dead-time generator comprising a circuit internal to the integrated circuit having an external terminal at which a dead-time setting component is connected, and wherein the dead-time generator comprises a circuit for providing a discrete dead-time for a range of dead-time setting values at the dead-time setting terminal and wherein, for a plurality of ranges of dead-time setting values at the dead-time setting terminal, the dead-time generator generates an associated plurality of discrete dead-times.

摘要翻译： 一种用于集成在集成电路中的死区时间发生器，其中所述集成电路包括高侧和低侧栅极驱动器，并且其中所述高侧和低侧栅极驱动器驱动输出开关使得在导通时间之间提供死区时间 输出开关，所述死区时间发生器包括所述集成电路内部的电路，所述电路具有连接死区时间设置组件的外部端子，并且其中所述死区时间发生器包括用于为 死区时间设定终端的死区时间设定值的范围，其中，对于死区时间设定终端的死区时间设定值的多个范围，死区时间发生器生成相关的多个离散死时间 。

公开(公告)号：US08022682B2

公开(公告)日：2011-09-20

申请号：US11741070

申请日：2007-04-27

申请人： Jun Honda ,  Xiao-chang Cheng

发明人： Jun Honda ,  Xiao-chang Cheng

IPC分类号： G05F1/00

CPC分类号： H02M1/36 ,  H02M3/156 ,  Y10S323/901 ,  Y10S323/908

摘要： A circuit for minimizing voltage inrush upon startup in a switching power converter having a switching stage including high and low switches connected at a common node, a feedback loop for maintaining a target output voltage, an output capacitor connected between an output node and the ground, an inductor connected between the common node and the output node, and a control circuit having a first error amplifier for providing a first signal based on a comparison of a reference voltage and voltage provided by the feedback loop, the control circuit including a level switch connected between the ground and the common node, the level switch being controlled in accordance with the first signal, wherein a large inrush current flowing into the output capacitor when the circuit is starting up is minimized.

摘要翻译： 一种用于在具有包括连接在公共节点上的高低开关的开关级的开关电源转换器中启动时的电压最小化的电路，用于维持目标输出电压的反馈回路，连接在输出节点和地之间的输出电容器， 连接在所述公共节点和所述输出节点之间的电感器，以及控制电路，具有第一误差放大器，用于基于由所述反馈回路提供的参考电压和电压的比较来提供第一信号，所述控制电路包括连接的电平开关 在接地和公共节点之间，根据第一信号控制电平开关，其中当电路启动时流入输出电容器的大的涌入电流被最小化。

公开(公告)号：US20070252566A1

公开(公告)日：2007-11-01

申请号：US11741070

申请日：2007-04-27

申请人： Jun Honda ,  Xiao-chang Cheng

发明人： Jun Honda ,  Xiao-chang Cheng

IPC分类号： G05F1/00

CPC分类号： H02M1/36 ,  H02M3/156 ,  Y10S323/901 ,  Y10S323/908

摘要： A circuit for minimizing voltage inrush upon startup in a switching power converter having a switching stage including high and low switches connected at a common node, a feedback loop for maintaining a target output voltage, an output capacitor connected between an output node and the ground, an inductor connected between the common node and the output node, and a control circuit having a first error amplifier for providing a first signal based on a comparison of a reference voltage and voltage provided by the feedback loop, the control circuit including a level switch connected between the ground and the common node, the level switch being controlled in accordance with the first signal, wherein a large inrush current flowing into the output capacitor when the circuit is starting up is minimized.

摘要翻译： 一种用于在具有包括连接在公共节点上的高低开关的开关级的开关电源转换器中启动时的电压最小化的电路，用于维持目标输出电压的反馈回路，连接在输出节点和地之间的输出电容器， 连接在所述公共节点和所述输出节点之间的电感器，以及控制电路，具有第一误差放大器，用于基于由所述反馈回路提供的参考电压和电压的比较来提供第一信号，所述控制电路包括连接的电平开关 在接地和公共节点之间，根据第一信号控制电平开关，其中当电路启动时流入输出电容器的大的涌入电流被最小化。

公开(公告)号：US20050151568A1

公开(公告)日：2005-07-14

申请号：US11013973

申请日：2004-12-16

申请人： Jun Honda ,  Xiao-chang Cheng

发明人： Jun Honda ,  Xiao-chang Cheng

IPC分类号： H03K19/0175 ,  H03B1/00 ,  H03F3/213 ,  H03F3/217 ,  H03K17/00 ,  H03K17/16 ,  H03K17/687

CPC分类号： H03F3/2171 ,  H03K17/16 ,  H03K17/6871

摘要： A control terminal driver IC for a switching circuit having series connected high and low side output transistors, an associated split power supply and a floating input, the gate drive IC, an exemplary, but non-limiting, example of which is a Class D audio amplifier. The IC includes an input circuit, a voltage to current converter connected to the input circuit, a level shifter formed in a mid well of the IC, which is operative to transfer the input signal to the low side without the need for a power supply input to the mid well, a current to voltage converter on the low side coupled to the level shifter; and an output circuit which is operative to generate control terminal drive signals for the high and low side transistors.

摘要翻译： 具有串联连接的高低侧输出晶体管的开关电路的控制端子驱动器IC，相关联的分离电源和浮动输入，栅极驱动IC，其示例性但非限制性示例是D类音频 放大器 IC包括输入电路，连接到输入电路的电压到电流转换器，形成在IC的中间阱中的电平转换器，其可操作以将输入信号传送到低侧而不需要电源输入 在中间阱中，耦合到电平移位器的低压侧的电流至电压转换器; 以及输出电路，其用于产生用于高侧和低侧晶体管的控制端驱动信号。

公开(公告)号：US07724054B2

公开(公告)日：2010-05-25

申请号：US11221240

申请日：2005-09-06

申请人： Jun Honda ,  Xiao-Chang Cheng

发明人： Jun Honda ,  Xiao-Chang Cheng

IPC分类号： H03K7/08

CPC分类号： H03K17/08122 ,  H03K5/1515 ,  H03K19/0013

摘要： A dead-time generator for incorporation in an integrated circuit wherein the integrated circuit includes a high side and low side gate driver and wherein the high side and low side gate driver drive output switches such that a dead-time is provided between on times of the output switches, the dead-time generator comprising a circuit internal to the integrated circuit having an external terminal at which a dead-time setting component is connected, and wherein the dead-time generator comprises a circuit for providing a discrete dead-time for a range of dead-time setting values at the dead-time setting terminal and wherein, for a plurality of ranges of dead-time setting values at the dead-time setting terminal, the dead-time generator generates an associated plurality of discrete dead-times.

摘要翻译： 一种用于集成在集成电路中的死区时间发生器，其中所述集成电路包括高侧和低侧栅极驱动器，并且其中所述高侧和低侧栅极驱动器驱动输出开关使得在导通时间之间提供死区时间 输出开关，所述死区时间发生器包括所述集成电路内部的电路，所述电路具有连接死区时间设置组件的外部端子，并且其中所述死区时间发生器包括用于为 死区时间设定终端的死区时间设定值的范围，其中，对于死区时间设定终端的死区时间设定值的多个范围，死区时间发生器生成相关的多个离散死时间 。

公开(公告)号：US07528651B2

公开(公告)日：2009-05-05

申请号：US11744960

申请日：2007-05-07

申请人： Jun Honda ,  Xiao-chang Cheng

发明人： Jun Honda ,  Xiao-chang Cheng

IPC分类号： H03F3/38

CPC分类号： H03F3/217 ,  H03F1/26 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/372

摘要： An integrated noise isolation circuit on a single silicon substrate die having a structural arrangement that minimizes noise. The integrated circuit including a noise sensitive circuit including an input stage; a noise generating circuit including an output stage; at least one high voltage level shift circuit coupling the noise generating and noise sensitive circuits for transferring a signal from the input to the output stage; and at least one floating structure for isolating influence of the noise.

摘要翻译： 在单个硅衬底管芯上的集成噪声隔离电路，具有使噪声最小化的结构布置。 所述集成电路包括包括输入级的噪声敏感电路; 包括输出级的噪声产生电路; 耦合所述噪声产生和噪声敏感电路的至少一个高电压电平移位电路，用于将信号从所述输入传送到所述输出级; 以及用于隔离噪声影响的至少一个浮动结构。

公开(公告)号：US07116136B2

公开(公告)日：2006-10-03

申请号：US11013973

申请日：2004-12-16

申请人： Jun Honda ,  Xiao-chang Cheng

发明人： Jun Honda ,  Xiao-chang Cheng

IPC分类号： H03B1/00 ,  H03L5/00

CPC分类号： H03F3/2171 ,  H03K17/16 ,  H03K17/6871

摘要： A control terminal driver IC for a switching circuit having series connected high and low side output transistors, an associated split power supply and a floating input, the gate drive IC, an exemplary, but non-limiting, example of which is a Class D audio amplifier. The IC includes an input circuit, a voltage to current converter connected to the input circuit, a level shifter formed in a mid well of the IC, which is operative to transfer the input signal to the low side without the need for a power supply input to the mid well, a current to voltage converter on the low side coupled to the level shifter; and an output circuit which is operative to generate control terminal drive signals for the high and low side transistors.

摘要翻译： 具有串联连接的高低侧输出晶体管的开关电路的控制端子驱动器IC，相关联的分离电源和浮动输入，栅极驱动IC，其示例性但非限制性示例是D类音频 放大器 IC包括输入电路，连接到输入电路的电压到电流转换器，形成在IC的中间阱中的电平转换器，其可操作以将输入信号传送到低侧而不需要电源输入 在中间阱中，耦合到电平移位器的低压侧的电流至电压转换器; 以及输出电路，其用于产生用于高侧和低侧晶体管的控制端驱动信号。