公开(公告)号：US08952839B2

公开(公告)日：2015-02-10

申请号：US13732113

申请日：2012-12-31

申请人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

发明人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

IPC分类号： H03M1/38 ,  H03K5/24 ,  H03M1/12 ,  H03M1/00 ,  H03M1/80 ,  H03M1/06

CPC分类号： H03M1/38 ,  H03K5/24 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/466 ,  H03M1/804

摘要： A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

摘要翻译： 电路包括比较器，其包括第一输入端，第二输入端和输出端。 电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。 多个电容性采样电路中的每一个包括第一和第二电容器，并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。 多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合，以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。

公开(公告)号：US20140184435A1

公开(公告)日：2014-07-03

申请号：US13732113

申请日：2012-12-31

申请人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

发明人： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen ,  Jinwen Xiao

IPC分类号： H03M1/38 ,  H03K5/24

CPC分类号： H03M1/38 ,  H03K5/24 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/466 ,  H03M1/804

摘要： A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

摘要翻译： 电路包括比较器，其包括第一输入端，第二输入端和输出端。 电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。 多个电容性采样电路中的每一个包括第一和第二电容器，并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。 多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合，以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。

公开(公告)号：US07902627B2

公开(公告)日：2011-03-08

申请号：US12414387

申请日：2009-03-30

申请人： Zhiwei Dong ,  Shouli Yan ,  Axel Thomsen ,  William W. K. Tang ,  Ka Y. Leung

发明人： Zhiwei Dong ,  Shouli Yan ,  Axel Thomsen ,  William W. K. Tang ,  Ka Y. Leung

IPC分类号： H01L25/00

CPC分类号： H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49096 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03K17/689 ,  H04L5/14 ,  H04L25/0268 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level.

摘要翻译： 一种具有电压隔离能力的集成电路，包括集成电路的第一电隔离区域，其包含用于处理数据流的第一组功能电路。 位于集成电路的基板中的第一组功能电路。 位于集成电路的导电层中的电容隔离电路在第一组功能电路之间提供高电压隔离连接，以及通过电容隔离电路连接到集成电路的第二组功能电路。 电容隔离电路包括用于经由电容隔离电路将差分信号中的数据传送到第二组功能电路的差分发射器。 差分接收器经由电容隔离电路从第二组功能电路接收差分信号内的数据。 差分接收器内的检测器电路检测接收到的数据。 当响应于差分信号产生的电压超过可编程电压阈值电平时，检测器电路监视差分信号并产生第一逻辑输出，并且当响应于差分信号产生的电压低于可编程电压阈值电平时产生第二逻辑输出 。

公开(公告)号：US08203370B2

公开(公告)日：2012-06-19

申请号：US12494621

申请日：2009-06-30

申请人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

发明人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

IPC分类号： H03K3/00

CPC分类号： H03K3/3565 ,  H03K5/088

摘要： A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

摘要翻译： 施密特触发器包括第一和第二电路。 第一电路接收输入电压并且响应于输入电压和第一偏置电压在逻辑“低”或逻辑“高”电压电平提供输出电压。 第二电路连接到第一电路以产生用于产生输出电压的第二偏置电流。 第二偏置电流大于第一偏置电流。 施密特触发器仅在第一偏置电压下工作在低功耗工作模式，以将逻辑“低”电压电平或逻辑“高”电压电平维持在基本恒定的水平。 在高功率工作模式下，施密特触发器在逻辑“低”电压电平和逻辑“高”电压电平之间的过渡期间使用第二偏置电压。

公开(公告)号：US08198951B2

公开(公告)日：2012-06-12

申请号：US12414379

申请日：2009-03-30

申请人： Zhiwei Dong ,  Shouli Yan ,  Axel Thomsen ,  William W. K. Tang ,  Ka Y. Leung

发明人： Zhiwei Dong ,  Shouli Yan ,  Axel Thomsen ,  William W. K. Tang ,  Ka Y. Leung

IPC分类号： H04B3/28 ,  H01P5/02

CPC分类号： H04B3/02 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K5/135 ,  H03K17/689 ,  H03M9/00 ,  H04L5/14 ,  H04L25/0266 ,  H04L25/0268 ,  H04L25/0272 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link. A differential transmitter on each of the plurality of communications channels transmits the data on the first link at a selected one of a first phase and a second phase and for transmitting the data on the second link at the selected one of the first phase and the second phase. The second phase is 180 degrees out of phase with the first phase. Each of the differential transmitters controls the selection of the first phase and the second phase on each of the first link and the second link such that only the first phase or the second phase is cross coupled onto a selected communications channel from adjacent communications channels.

摘要翻译： 具有电压隔离能力的集成电路包括用于从集成电路收发数据的多个通信信道。 每个通信信道包括位于集成电路的导电层中的电容隔离电路，用于提供高电压隔离链路。 电容隔离电路在电容隔离电路中的第一链路和第二链路上跨第一组电容器分配高电压隔离信号的第一部分，并且将第二部分高电压隔离信号分配到第二组电容器 在电容隔离电路中的第一链路和第二链路中。 多个通信信道中的每一个上的差分接收机在第一链路和第二链路上接收数据。 多个通信信道中的每一个上的差分发射机以第一相位和第二相位中的所选择的一个在第一链路上发送数据，并且用于在第一和第二相位中选定的一个的第二链路上发送数据 相。 第二阶段与第一阶段相差180度。 每个差分发射机控制在第一链路和第二链路中的每一个上的第一相位和第二相位的选择，使得只有第一相位或第二相位相互耦合到来自相邻通信信道的所选择的通信信道上。

公开(公告)号：US20140333465A1

公开(公告)日：2014-11-13

申请号：US13892235

申请日：2013-05-10

申请人： Mohamed Elsayed ,  Xiaodong Wang ,  Shouli Yan

发明人： Mohamed Elsayed ,  Xiaodong Wang ,  Shouli Yan

IPC分类号： H03M1/12

CPC分类号： H03M1/0845 ,  H03M1/466

摘要： A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

摘要翻译： 电压参考电路包括包括第一端子并且包括耦合到电源节点的第二端子的电容器。 电压参考电路还包括放大器，第一晶体管和开关。 放大器包括被配置为接收参考电压输入信号的第一输入，被配置为接收反馈信号的第二输入和输出。 第一晶体管包括耦合到放大器的第二输入端和输出节点的源极，耦合到电容器的栅极和漏极。 第一晶体管被配置为基于由电容器提供给栅极的电荷在源极处提供参考电压。 开关包括耦合到放大器的输出的第一端子，并且包括耦合到电容器的第一端子的第二端子。

公开(公告)号：US08922418B2

公开(公告)日：2014-12-30

申请号：US13892235

申请日：2013-05-10

申请人： Mohamed Elsayed ,  Xiaodong Wang ,  Shouli Yan

发明人： Mohamed Elsayed ,  Xiaodong Wang ,  Shouli Yan

IPC分类号： H03M1/12

CPC分类号： H03M1/0845 ,  H03M1/466

摘要： A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

摘要翻译： 电压参考电路包括包括第一端子并且包括耦合到电源节点的第二端子的电容器。 电压参考电路还包括放大器，第一晶体管和开关。 放大器包括被配置为接收参考电压输入信号的第一输入，被配置为接收反馈信号的第二输入和输出。 第一晶体管包括耦合到放大器的第二输入端和输出节点的源极，耦合到电容器的栅极和漏极。 第一晶体管被配置为基于由电容器提供给栅极的电荷在源极处提供参考电压。 开关包括耦合到放大器的输出的第一端子，并且包括耦合到电容器的第一端子的第二端子。

公开(公告)号：US09041569B2

公开(公告)日：2015-05-26

申请号：US13931767

申请日：2013-06-28

申请人： Yan Zhou ,  Clayton Daigle ,  Shouli Yan ,  Mohamed Elsayed

发明人： Yan Zhou ,  Clayton Daigle ,  Shouli Yan ,  Mohamed Elsayed

IPC分类号： H03M1/06

CPC分类号： H03M1/0617 ,  H03M1/1047 ,  H03M1/466

摘要： A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.

摘要翻译： 逐次逼近寄存器（SAR）ADC包括包括第一和第二输入，控制输入以及第一和第二输出的SAR比较器电路。 SAR比较器电路还包括耦合到第一和第二输入的多个电容器，并且包括被配置为将多个电容器耦合到第一电压和第二电压中的一个的多个开关。 SAR ADC还包括耦合到第一和第二输出和SAR比较器的控制输入的校准电路。 校准电路被配置为控制多个开关以选择性地将多个电容器耦合到第一和第二电压之一，以向SAR比较器电路提供校准信号。 校准电路被配置为基于在第一和第二输出处的相应输出信号校准SAR比较器。

公开(公告)号：US08384573B2

公开(公告)日：2013-02-26

申请号：US12122368

申请日：2008-05-16

申请人： Xiaohong Li ,  Shouli Yan ,  Zhiheng Cao

发明人： Xiaohong Li ,  Shouli Yan ,  Zhiheng Cao

IPC分类号： H03M3/00

CPC分类号： H03M3/504 ,  H03F3/2175

摘要： A digital-to-analog converter (DAC) with a digital segment having a digital data input and an analog segment coupled to the digital segment and having an analog output to output an analog signal corresponding to the digital data. The analog segment includes one or more gain stages and a feedback structure to couple the analog output to the one or more gain stages to attenuate signal distortion at the analog output. A combined gain of the one or more gain stages determines a signal distortion attenuation characteristic of the analog segment.

摘要翻译： 具有数字分段的数模转换器（DAC）具有数字数据输入和耦合到数字段的模拟分段并且具有模拟输出以输出对应于数字数据的模拟信号。 模拟段包括一个或多个增益级和用于将模拟输出耦合到一个或多个增益级的反馈结构，以衰减模拟输出处的信号失真。 一个或多个增益级的组合增益确定模拟段的信号失真衰减特性。

公开(公告)号：US09874887B2

公开(公告)日：2018-01-23

申请号：US13404981

申请日：2012-02-24

申请人： Shouli Yan ,  Alan Westwick

发明人： Shouli Yan ,  Alan Westwick

IPC分类号： G05F1/00 ,  G05F1/565

CPC分类号： G05F1/565

摘要： A voltage regulator circuit with variable feedback is disclosed. In one embodiment, a voltage regulator includes an amplifier having a first input configured to receive a reference voltage and a second input configured to receive a feedback signal. The voltage regulator further includes first and second transistors each having respective gate terminals coupled to an output of the amplifier. A resistor network coupled to the second input of the amplifier and further coupled to the first and second transistors. The resistor network is configured to produce the feedback signal based on currents through the first and second transistors, respectively.