公开(公告)号：US10712770B1

公开(公告)日：2020-07-14

申请号：US16042785

申请日：2018-07-23

Applicant: Xilinx, Inc.

Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Arianne B. Roldan ,  Nakul Narang ,  Yipeng Wang ,  Yohan Frans ,  Kun-Yung Chang

IPC: G06F1/12 ,  G06F1/10 ,  H03K19/018 ,  H04J3/06 ,  G06F13/16 ,  G11C7/22

Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

公开(公告)号：US09729170B1

公开(公告)日：2017-08-08

申请号：US15193635

申请日：2016-06-27

Applicant: Xilinx, Inc.

Inventor： Arianne B. Roldan ,  Hsung Jai Im

IPC: H03M9/00 ,  H04L27/04

CPC classification number: H03M9/00 ,  H04L27/04

Abstract: An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.