公开(公告)号：US09729153B1

公开(公告)日：2017-08-08

申请号：US15234640

申请日：2016-08-11

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K19/096 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

CPC classification number: H03K19/1737 ,  H03K19/1776 ,  H03K19/20

Abstract: A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in response to a configuration signal, the output circuit between the latch mode and the pass-through mode.

公开(公告)号：US10069486B1

公开(公告)日：2018-09-04

申请号：US15196466

申请日：2016-06-29

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Ilya K. Ganusov

IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/037

Abstract: A register circuit includes a first pulse-latch circuit configured to store data from a first input node. A multiplexer circuit is configured to select between an output of the first pulse-latch circuit and a second input node. A second pulse-latch circuit is configured to store data provided by the multiplexer circuit. A control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a dual-latch mode.

公开(公告)号：US09118310B1

公开(公告)日：2015-08-25

申请号：US14482832

申请日：2014-09-10

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K19/177 ,  H03K5/14 ,  H03K5/135 ,  H03K19/173

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03K5/15006 ,  H03K5/156 ,  H03K19/1737 ,  H03K19/17748

Abstract: A programmable delay circuit block includes an input stage having a cascade input and a clock input, wherein the input stage passes a signal received at the cascade input or a signal received at the clock input. The programmable delay circuit block further may include a delay block configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage and a pulse generator configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block also includes an output stage having a cascade output and a clock output. The output stage is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output and pass the signal received at the clock input, the inverted version of the pulse signal, or the delayed signal from the clock output.

Abstract translation: 可编程延迟电路块包括具有级联输入和时钟输入的输入级，其中输入级通过在级联输入处接收的信号或在时钟输入处接收的信号。 可编程延迟电路块还可以包括延迟块，其被配置为通过对从输入级传递的信号施加选定量的延迟来产生延迟信号;以及脉冲发生器，被配置为产生脉冲信号，脉冲信号具有取决于 拖延量 可编程延迟电路块还包括具有级联输出和时钟输出的输出级。 输出级被配置为使来自级联输出的脉冲信号或延迟信号的反转版本通过，并且传递在时钟输入处接收到的信号，脉冲信号的反相形式或来自时钟输出的延迟信号。

公开(公告)号：US20170373692A1

公开(公告)日：2017-12-28

申请号：US15191288

申请日：2016-06-23

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Rafael C. Camarota

IPC: H03K19/177 ,  G01R31/3177 ,  G01R31/317

CPC classification number: H03K19/17792 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318583 ,  G01R31/31937 ,  H03K19/17728 ,  H03K19/1776

Abstract: A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.

公开(公告)号：US09577615B1

公开(公告)日：2017-02-21

申请号：US14792894

申请日：2015-07-07

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K3/017 ,  H03K3/356

CPC classification number: H03K3/356156 ,  G06F1/10 ,  H03K5/1565

Abstract: A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit coupled to an output of a circuit element and generating a pulsed output coupled to a clock input of a register of the pulse-controlled register circuit; wherein the pulsed output is coupled to the clock input of the register to enable the pulse-controlled register circuit to store data at a time that is different than an edge of the clock signal. A method of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is also described.

Abstract translation: 描述了实现双边沿时钟的集成电路中减小占空比失真的电路。 电路还包括多个电路元件，其能够路由在电路元件的输出处产生的数据; 多个寄存器电路，用于在多个电路元件的输出端存储数据; 将时钟信号路由到多个寄存器电路的时钟输入的时钟电路; 以及脉冲控制寄存器电路，其耦合到电路元件的输出并且产生耦合到所述脉冲控制寄存器电路的寄存器的时钟输入的脉冲输出; 其中所述脉冲输出耦合到所述寄存器的时钟输入，以使所述脉冲控制寄存器电路在与所述时钟信号的边沿不同的时间存储数据。 还描述了实现双边沿时钟的集成电路中减少占空比失真的方法。

公开(公告)号：US09537491B1

公开(公告)日：2017-01-03

申请号：US14667580

申请日：2015-03-24

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03L7/06 ,  H03L7/08

CPC classification number: H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  H03K5/15006 ,  H03K5/1502 ,  H03K19/1774

Abstract: Methods and apparatus for generating multiple phase-shifted clock signals from a base clock signal using programmable delays at the leaf level in a clock distribution network are described. One example method for generating and distributing multiple phase-shifted clock signals in a programmable integrated circuit (IC) generally includes generating a base clock signal, routing the base clock signal through a clock distribution network in the programmable IC to a leaf node, and applying one or more programmable delays to the base clock signal received from the leaf node to generate the multiple phase-shifted clock signals.

Abstract translation: 描述了使用在时钟分配网络中的叶级的可编程延迟从基本时钟信号产生多个相移时钟信号的方法和装置。 用于在可编程集成电路（IC）中生成和分配多个相移时钟信号的一个示例性方法通常包括生成基本时钟信号，将基准时钟信号通过可编程IC中的时钟分配网络路由到叶节点，以及应用 从叶节点接收的基本时钟信号的一个或多个可编程延迟以产生多个相移时钟信号。

公开(公告)号：US10230374B1

公开(公告)日：2019-03-12

申请号：US15267572

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K19/177 ,  H03K3/037 ,  G06F17/50

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits preventing hold violations in clock synchronized circuits. In an example implementation, a circuit includes a logic circuit having a set of inputs. Signal propagation time on a signal path to at least one of the set of inputs presents a hold violation. The circuit includes first and second level-sensitive latches. The first level-sensitive latch has an output connected to the one of the plurality of inputs. The second level-sensitive latch has an input connected to an output of the logic circuit. A latch control circuit is configured to remove the hold violation on the input by providing a pulsed clock signal to a clock input of the second level-sensitive latch and an inversion of the pulsed clock signal to a clock input of the first level-sensitive latch.

公开(公告)号：US10069497B2

公开(公告)日：2018-09-04

申请号：US15191288

申请日：2016-06-23

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Rafael C. Camarota

IPC: H03K19/177 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.

公开(公告)号：US09954534B2

公开(公告)日：2018-04-24

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H01L25/00 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

公开(公告)号：US20180083633A1

公开(公告)日：2018-03-22

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.