公开(公告)号：US20110003254A1

公开(公告)日：2011-01-06

申请号：US12829437

申请日：2010-07-02

Applicant: Yao-Wen Chang ,  Huang-Yu Chen

Inventor： Yao-Wen Chang ,  Huang-Yu Chen

IPC: G03F7/20

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: A layout decomposition method, applicable to a double pattern lithography, includes the steps of: putting at least a stitch on each of a plurality of sub-patterns of an initial layout pattern at preset intervals to thereby divide the each of the plurality of sub-patterns into a plurality of unit blocks each selectively labeled as a first region or a second region such that the first region and the second region in same said sub-pattern alternate, wherein any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, are labeled as the first region and the second region, respectively; reducing the stitches of any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, so as to generate a first layout pattern having a minimum number of stitches; and reducing the stitches of any two contiguous ones of said unit blocks of each of said sub-patterns in the first layout pattern, so as to generate a second layout pattern having a minimum number of stitches.

Abstract translation: 适用于双模式光刻的布局分解方法包括以下步骤：以预设的间隔将初始布局图案的多个子图案中的每一个以至少一个针迹进行布置，从而将多个子图案中的每一个划分， 模式分成多个单元块，每个单元块选择性地标记为第一区域或第二区域，使得相同的所述子图案中的第一区域和第二区域交替，其中归因于任何两个相邻的单元块中的任何两个相邻单元块 分别标记为第一区域和第二区域; 分别归因于任何两个相邻的子图案的所述单元块中的任何两个相邻的单元块的线圈，以便生成具有最小线数的第一布局图案; 以及减少在所述第一布局图案中的每个所述子图案的所述单元块中的任何两个相邻的所述单元块的针迹，以便生成具有最小线数的第二布局图案。

公开(公告)号：US08453095B2

公开(公告)日：2013-05-28

申请号：US13176823

申请日：2011-07-06

Applicant: Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

Inventor： Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5077 ,  G06F17/5081

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

Abstract translation: 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感 基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线 模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

公开(公告)号：US20120091592A1

公开(公告)日：2012-04-19

申请号：US12907640

申请日：2010-10-19

Applicant: Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC: H01L29/41 ,  H01L21/283 ,  G06F17/50 ,  G03F7/20 ,  G03F1/00

CPC classification number: H01L21/0337

Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

Abstract translation: 形成集成电路结构的方法包括形成平行于第一方向和晶片表示的第一和第二多个轨道。 以交替模式分配第一和第二多个轨道。 第一多个图案布置在第一多个轨道上，而不是在第二多个轨道上。 第二多个图案布置在第二多个轨道上而不是在第一多个轨道上。 第一多个图案在垂直于第一方向的第一方向和第二方向上延伸，使得第二多个图案中的每一个被第一多个图案的部分包围，并且基本上没有相邻的图案 晶片表面上的第一多个图案具有大于预定间距的间隔。

公开(公告)号：US08907441B2

公开(公告)日：2014-12-09

申请号：US12702885

申请日：2010-02-09

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

IPC: H01L21/70 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract translation: 半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。 单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。 在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

公开(公告)号：US08448100B1

公开(公告)日：2013-05-21

申请号：US13444158

申请日：2012-04-11

Applicant: Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

Inventor： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G03F1/70

Abstract: A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

Abstract translation: 计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。 专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。

公开(公告)号：US20110119648A1

公开(公告)日：2011-05-19

申请号：US12649979

申请日：2009-12-30

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

Abstract translation: 一种方法包括接收要包括在IC布局中的多个电路部件的标识。 生成表示连接两个电路部件的第一图案的数据。 第一图案具有多个片段。 至少两个片段具有彼此垂直的纵向方向。 保留与至少两个段中的至少一个相邻的至少一个无图案区域。 生成表示在第一图案附近的一个或多个附加图案的数据。 在无模式区域中没有形成附加图案。 第一种图案和附加图案形成双重图案化顺应的图案集合。 将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

公开(公告)号：US08601408B2

公开(公告)日：2013-12-03

申请号：US13269757

申请日：2011-10-10

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

公开(公告)号：US08418111B2

公开(公告)日：2013-04-09

申请号：US12953661

申请日：2010-11-24

Applicant: Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

Inventor： Huang-Yu Chen ,  Fang-Yu Fan ,  Yuan-Te Hou ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Lee Fung Song ,  Wen-Chun Huang ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.

Abstract translation: 提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。 示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。 如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。 如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有 彩色图案布局的特点。 每个面具都包含单一颜色的特征。

公开(公告)号：US08239806B2

公开(公告)日：2012-08-07

申请号：US12649979

申请日：2009-12-30

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

Abstract translation: 一种方法包括接收要包括在IC布局中的多个电路部件的标识。 生成表示连接两个电路部件的第一图案的数据。 第一图案具有多个片段。 至少两个片段具有彼此垂直的纵向方向。 保留与至少两个段中的至少一个相邻的至少一个无图案区域。 生成表示在第一图案附近的一个或多个附加图案的数据。 在无模式区域中没有形成附加图案。 第一种图案和附加图案形成双重图案化顺应的图案集合。 将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

公开(公告)号：US20110072405A1

公开(公告)日：2011-03-24

申请号：US12831982

申请日：2010-07-07

Applicant: Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207

Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.

Abstract translation: 在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。 生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。 切割线将芯片表示划分成多个电路区域。 多个电路区域相对于第一IP的位置向外偏移以产生空间。 第一个IP被吹入空间，产生一个IP地址。 然后执行直接收缩。