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1.发明授权Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses 有权用于通过使用脉冲通过无线电发送数据的发送器电路和无线电发送装置公开(公告)号：US08054908B2
公开(公告)日：2011-11-08
申请号：US11987703
申请日：2007-12-04
Applicant: Yasuhiro Nakasha , Yoichi Kawano
Inventor： Yasuhiro Nakasha , Yoichi Kawano
IPC: H04L27/00
CPC classification number: H04L27/04 , H04B1/71635 , H04B1/7172 , H04B1/7174 , H04L25/4902
Abstract: A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.
Abstract translation: 通过使用脉冲发送数据的发送器电路具有可变延迟电路和逻辑电路。 可变延迟电路采用时钟作为输入，并根据数据延迟时钟。 逻辑电路将时钟和可变延迟电路的输出作为输入，并通过在时钟和可变延迟电路的输出之间执行逻辑运算来输出脉冲。
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公开(公告)号：US07612709B2
公开(公告)日：2009-11-03
申请号：US12175081
申请日：2008-07-17
Applicant: Yoichi Kawano , Yasuhiro Nakasha
Inventor： Yoichi Kawano , Yasuhiro Nakasha
IPC: G01S13/08
Abstract: A radar device has a clock generator (131) generating a base clock; a transmitter (121 to 125) transmitting transmission pulses as gradually increasing a displacement amount with respect to each edge of the base clock; and a receiver (101 to 106) receiving reflected waves of the transmitted transmission pulses in synchronization with the edges of the base clock.
Abstract translation: 雷达装置具有产生基准时钟的时钟发生器（131） 发送器（121至125），其相对于所述基本时钟的每个边缘逐渐增加位移量，发送发送脉冲; 以及与基准时钟的边沿同步地接收所发送的发送脉冲的反射波的接收器（101至106）。
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3.发明申请Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses 有权用于通过使用脉冲通过无线电发送数据的发送器电路和无线电发送装置
公开(公告)号：US20080198939A1
公开(公告)日：2008-08-21
申请号：US11987703
申请日：2007-12-04
Applicant: Yasuhiro Nakasha , Yoichi Kawano
Inventor： Yasuhiro Nakasha , Yoichi Kawano
IPC: H04L27/00
CPC classification number: H04L27/04 , H04B1/71635 , H04B1/7172 , H04B1/7174 , H04L25/4902
Abstract: A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.
Abstract translation: 通过使用脉冲发送数据的发送器电路具有可变延迟电路和逻辑电路。 可变延迟电路采用时钟作为输入，并根据数据延迟时钟。 逻辑电路将时钟和可变延迟电路的输出作为输入，并通过在时钟和可变延迟电路的输出之间执行逻辑运算来输出脉冲。
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公开(公告)号：US08891599B2
公开(公告)日：2014-11-18
申请号：US13163902
申请日：2011-06-20
Applicant: Yasuhiro Nakasha
Inventor： Yasuhiro Nakasha
Abstract: A transmission and reception apparatus includes: a transmitter circuit to transmit to an object a transmission signal including a comb-shaped wave in which a first plurality of pulses are arranged in a comb shape; and a receiver circuit to receive a reflection signal based on the transmission signal.
Abstract translation: 发送和接收装置包括：发送器电路，向对象发送包括梳状波的发送信号，其中第一多个脉冲以梳状布置; 以及接收电路，用于基于发送信号接收反射信号。
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公开(公告)号：US08437423B2
公开(公告)日：2013-05-07
申请号：US12577289
申请日：2009-10-12
Applicant: Yasuhiro Nakasha
Inventor： Yasuhiro Nakasha
IPC: H04L27/00
CPC classification number: H04L25/4902 , H03K5/06 , H04L27/02
Abstract: A transmission device including a pulse generating section configured to generate a plurality of pulses using a signal of data and a signal obtained by delaying the signal of data, and to adjust the pulse width such that each of the plurality of pulses has a pulse width conforming to a sequence of the data; a band-pass filter filtering the plurality of pulses; and a transmission amplifier amplifying the filtered plurality of pulses and outputting the filtered plurality of pulses as a transmission signal.
Abstract translation: 一种发送装置，包括：脉冲发生部，被配置为使用数据的信号和通过延迟数据的信号而获得的信号产生多个脉冲，并且调整脉冲宽度，使得所述多个脉冲中的每一个具有符合脉冲宽度 到数据的序列; 滤波多个脉冲的带通滤波器; 以及发送放大器，放大经过滤波的多个脉冲，并将滤波的多个脉冲作为发送信号输出。
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6.发明授权Pulse transmission method, pulse transmission system, transmitter, and receiver 有权脉冲传输方式，脉冲传输系统，发射机和接收机
公开(公告)号：US08144761B2
公开(公告)日：2012-03-27
申请号：US12238952
申请日：2008-09-26
Applicant: Yasuhiro Nakasha
Inventor： Yasuhiro Nakasha
IPC: H04L27/00
CPC classification number: H04B1/7163 , H04B2001/6908 , H04L25/4902 , H04L25/4917
Abstract: A pulse transmission method for transmitting data by using pulse signals, each having a predetermined pulse width; defining a symbol time at least N times the predetermined pulse width, N being at least 2; defining a basic delay time calculated by dividing the predetermined pulse width by a predetermined integer; placing the pulse signals in the symbol time by delaying the pulse signals by an integral multiple of the basic delay time from start of the symbol time, the number of the pulse signals being k and 0≦k≦N being satisfied; and transmitting the pulse signals.
Abstract translation: 一种用于通过使用具有预定脉冲宽度的脉冲信号发送数据的脉冲发送方法; 将符号时间定义为至少预定脉冲宽度的N倍，N至少为2; 定义通过将预定脉冲宽度除以预定整数而计算的基本延迟时间; 通过将脉冲信号延迟从符号时间开始的基本延迟时间的整数倍，脉冲信号的数量为k和0＆nlE; k＆nlE; N被满足，将脉冲信号放在符号时间内; 并发送脉冲信号。
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7.发明申请
公开(公告)号：US20080204089A1
公开(公告)日：2008-08-28
申请号：US11987702
申请日：2007-12-04
Applicant: Yasuhiro Nakasha
Inventor： Yasuhiro Nakasha
IPC: H03B19/14
CPC classification number: H03B19/14
Abstract: A frequency dividing circuit has a master circuit and a slave circuit, and a load section in at least either one of the master and slave circuits is constructed to provide an impedance that decreases with increasing frequency.
Abstract translation: 分频电路具有主电路和从电路，并且主电路和从电路中的至少一个中的负载部分被构造成提供随频率增加而减小的阻抗。
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公开(公告)号：US08723716B2
公开(公告)日：2014-05-13
申请号：US13043593
申请日：2011-03-09
Applicant: Yasuhiro Nakasha
Inventor： Yasuhiro Nakasha
IPC: G01S13/00
CPC classification number: G01S7/292 , G01S13/887 , G01S13/89
Abstract: A communication device includes an oscillator to generate an oscillation signal; a harmonic generator to generate a higher harmonic wave from the oscillation signal; a first filter to take out a first high frequency signal; a second filter to take out a second high frequency signal; a down conversion mixer to use the second high frequency signal to perform down conversion of a signal obtained by receiving a reflected signal of the first high frequency signal; a hybrid coupler to generate a first intermediate frequency signal and a second intermediate frequency signal, which are orthogonal with each other; a first mixer to take out a first baseband signal by mixing an output from the down conversion mixer with the first intermediate frequency signal; and a second mixer to take out a second baseband signal by mixing an output from the down conversion mixer with the first intermediate frequency signal.
Abstract translation: 通信装置包括：振荡器，用于产生振荡信号; 谐波发生器从振荡信号产生高次谐波; 第一滤波器，用于取出第一高频信号; 第二滤波器，用于取出第二高频信号; 下变频混频器，用于使用第二高频信号对通过接收第一高频信号的反射信号而获得的信号进行下变频; 混合耦合器，用于产生彼此正交的第一中频信号和第二中频信号; 第一混频器，通过将来自下变频混频器的输出与第一中频信号进行混合来取出第一基带信号; 以及第二混频器，通过将来自下变频混频器的输出与第一中频信号进行混合来取出第二基带信号。
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公开(公告)号：US08311151B2
公开(公告)日：2012-11-13
申请号：US12401356
申请日：2009-03-10
Applicant: Yasuhiro Nakasha
Inventor： Yasuhiro Nakasha
IPC: H04L27/04
CPC classification number: H04B1/7174
Abstract: A radio transmission apparatus has a first duty adjustment circuit which changes a duty ratio of a clock signal, a second duty adjustment circuit which changes the duty ratio of the clock signal to a duty ratio different from the duty ratio of the clock signal changed by the first duty adjustment circuit, a first AND circuit which takes a logical product between a data signal and the clock signal having passed through the first duty adjustment circuit, and a second AND circuit which takes a logical product between an output signal of the first AND circuit and the clock signal having passed through inversion of the output of the second duty adjustment circuit to generate a pulse signal.
Abstract translation: 无线发送装置具有改变时钟信号的占空比的第一占空比调整电路，将时钟信号的占空比改变为与由时钟信号变化的时钟信号的占空比不同的占空比的第二占空比调整电路 第一占空比调整电路，第一AND电路，其采用数据信号和已经通过第一占空比调整电路的时钟信号之间的逻辑积;以及第二AND电路，其在第一AND电路的输出信号之间取逻辑积 并且时钟信号已通过第二占空比调整电路的输出的反相以产生脉冲信号。
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公开(公告)号：US20080012660A1
公开(公告)日：2008-01-17
申请号：US11606989
申请日：2006-12-01
Applicant: Yasuhiro Nakasha , Tatsuya Hirose
Inventor： Yasuhiro Nakasha , Tatsuya Hirose
IPC: H03H7/18
CPC classification number: H03H7/21 , H03H7/185 , H03H7/19 , H03H2007/0192
Abstract: A phase shifter circuit includes a plurality of first series circuits each comprised of a series connection of one capacitor and one resistor, a first circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of first series circuits in series, the first circuit element and the chain structure together constituting a first loop circuit, a plurality of second series circuits each comprised of a series connection of one capacitor and one resistor, a second circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of second series circuits in series, the second circuit element and the chain structure together constituting a second loop circuit, and a plurality of connection lines connecting between the first loop circuit and the second loop circuit.
Abstract translation: 一种移相器电路包括多个第一串联电路，每个第一串联电路由一个电容器和一个电阻器的串联连接构成，第一电路元件至少包括电感，该电感连接在链结构的第一端和第二端之间， 串联的第一串联电路，第一电路元件和链结构一起构成第一环路电路，多个第二串联电路，每个第二串联电路由一个电容器和一个电阻器的串联连接构成，第二电路元件至少包括电感连接 在通过串联连接多个第二串联电路而制成的链结构的第一端和第二端之间，第二电路元件和链结构一起构成第二环路电路，以及多个连接线，其连接在第一环路 电路和第二回路电路。
