公开(公告)号：US06751153B2

公开(公告)日：2004-06-15

申请号：US10187048

申请日：2002-06-28

申请人： Yasumichi Mori ,  Ken Sumitani ,  Yuji Tanaka ,  Haruyasu Fukui

发明人： Yasumichi Mori ,  Ken Sumitani ,  Yuji Tanaka ,  Haruyasu Fukui

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.

摘要翻译： 一种非易失性半导体存储器件，包括多个存储单元，每个存储单元包括多个存储器单元，用于识别外部输入的命令信号并输出​​识别信号的命令识别单元，用于产生用于执行的控制信号的内部控制单元 由识别信号指定的命令，地址控制部分，用于根据外部输入的地址信号，向包括要访问的多个存储体组的任意组合的存储区域产生内部地址信号;以及第一地址转换部分 用于反相或非反相输入地址信号的至少一个特定位的逻辑值，并将结果输入地址信号输出到地址控制部分。 基于控制信号和内部地址信号来访问预定的存储单元。

公开(公告)号：US06646947B2

公开(公告)日：2003-11-11

申请号：US10184133

申请日：2002-06-26

申请人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

发明人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

IPC分类号： G11C700

CPC分类号： G06F13/28

摘要： A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

摘要翻译： 本发明的数据传输控制装置包括：用于识别输入控制命令的命令识别部分; 第一地址输出部分，用于基于输入的控制命令来控制数据传送地址的输出和存储顺序以及数据传送完成地址; 第一存储器地址存储部分，用于存储从第一地址输出部分输出的第一存储器阵列的数据传输开始地址; 第二存储器地址存储部分，用于存储从第一地址输出部分输出的第二存储器阵列的数据传输开始地址; 第三存储器地址存储部分，用于存储从第一地址输出部分输出的数据传输完成地址。

公开(公告)号：US06549475B2

公开(公告)日：2003-04-15

申请号：US10183857

申请日：2002-06-25

申请人： Ken Nakazawa ,  Ken Sumitani ,  Haruyasu Fukui ,  Yasumichi Mori

发明人： Ken Nakazawa ,  Ken Sumitani ,  Haruyasu Fukui ,  Yasumichi Mori

IPC分类号： G11C1604

CPC分类号： G11C7/22

摘要： A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.

公开(公告)号：US20050174868A1

公开(公告)日：2005-08-11

申请号：US11051139

申请日：2005-02-04

申请人： Shinsuke Anzai ,  Yasumichi Mori

发明人： Shinsuke Anzai ,  Yasumichi Mori

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C13/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/3436 ,  G11C2013/0054 ,  G11C2213/31

摘要： A nonvolatile semiconductor memory device comprises a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.

摘要翻译： 非易失性半导体存储器件包括读出电路，其通过向所选择的存储单元施加预定电压来读取存储在所选择的存储单元中的数据，以及参考单元，使得可以流过对应于相应阈值电压的电流，并且比较流过 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。

公开(公告)号：US20070230245A1

公开(公告)日：2007-10-04

申请号：US10589066

申请日：2005-02-09

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C29/04

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/28 ,  G11C29/76 ,  G11C29/82

摘要： A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block, generates a dummy block address for selecting a dummy block that is different from the selected block address and a defective block address of a defective block by a predetermined logical operation targeted for a specific partial bit in address bits of the selected block address when the defective block is contained in the memory plane. A bit line connected to the selected memory cell selected by the selected block address and a bit line in the dummy block are connected to differential input terminals of a sense amplifier circuit 9.

摘要翻译： 根据本发明的半导体存储装置包括一个或多个包括多个存储器块9的存储器平面8和一个块选择电路，用于解码用于从存储器平面8中选择存储器块9的块地址信号，以选择存储器 块，产生一个虚拟块地址，用于当所选择的块地址的地址位中的特定部分位的目标地址为预定逻辑运算时，选择不同于所选择的块地址的虚拟块和缺陷块的缺陷块地址， 缺陷块包含在存储器平面中。 连接到由选择的块地址选择的所选存储单元的位线和伪块中的位线连接到读出放大器电路9的差分输入端。

公开(公告)号：US06947322B2

公开(公告)日：2005-09-20

申请号：US10630641

申请日：2003-07-29

申请人： Shinsuke Anzai ,  Yasumichi Mori ,  Hidehiko Tanaka

发明人： Shinsuke Anzai ,  Yasumichi Mori ,  Hidehiko Tanaka

IPC分类号： G06F12/16 ,  G11C11/56 ,  G11C16/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/04 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28 ,  G11C29/70 ,  G11C2211/5623 ,  G11C2211/5641

摘要： A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.

摘要翻译： 提供一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括二值存储区域和多值存储器区域，其中该二值存储器区域包括多个存储单元，每个存储器单元存储1位数据， 多值存储区包括多个存储2位或更多比特数据的存储单元，以及读出两值存储区域的数据和多值存储器区域的数据读出共同的读出放大器单元，用于读取数据 通过将所选择的存储器单元的电位与参考电位进行比较来存储在所选存储单元中。

公开(公告)号：US06442058B2

公开(公告)日：2002-08-27

申请号：US09834963

申请日：2001-04-13

申请人： Yasumichi Mori

发明人： Yasumichi Mori

IPC分类号： G11C1700

CPC分类号： G06F9/3822 ,  G06F9/26 ,  G06F9/261 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3814

摘要： A control circuit comprises an external command recognition section for recognizing an external command, the external command being an operation command input from outside the control circuit, an internal ROM bank including a plurality of storage regions, the internal ROM bank being used to store an internal code for achieving operations specified by the external command recognized by the external command recognition section, an internal ROM selection section for selecting a required storage region from the plurality of storage regions of the internal ROM bank in accordance with the external command recognized by the external command recognition section, a program counter for selecting and indicating an address of an internal command to be executed from a plurality of addresses of internal commands stored in the internal ROM bank, an internal command register for storing the internal command read from the internal ROM bank, and an internal command execution section for executing the internal command stored in the internal command register.

摘要翻译： 控制电路包括用于识别外部命令的外部命令识别部分，作为从控制电路外部输入的操作命令的外部命令，包括多个存储区域的内部ROM组，内部ROM组用于存储内部 用于实现由外部命令识别部识别的外部命令指定的操作的代码;内部ROM选择部分，用于根据由外部命令识别的外部命令从内部ROM组的多个存储区域中选择所需的存储区域 识别部分，用于从存储在内部ROM组中的多个内部命令的地址中选择和指示要执行的内部命令的地址的程序计数器，用于存储从内部ROM存储体读取的内部命令的内部命令寄存器， 以及用于执行in的内部命令执行部分 内部命令存储在内部命令寄存器中。

公开(公告)号：US07460419B2

公开(公告)日：2008-12-02

申请号：US10589101

申请日：2005-02-09

申请人： Yasumichi Mori ,  Masahiko Watanabe

发明人： Yasumichi Mori ,  Masahiko Watanabe

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76

摘要： A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.

摘要翻译： 根据本发明的非易失性半导体存储装置包括：块存储器替换装置，用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10，用于将输入的外部块地址转换为内部块地址，通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特，并且存储块5中的每一个被选择。

公开(公告)号：US07430144B2

公开(公告)日：2008-09-30

申请号：US10589066

申请日：2005-02-09

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/28 ,  G11C29/76 ,  G11C29/82

摘要： A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block, generates a dummy block address for selecting a dummy block that is different from the selected block address and a defective block address of a defective block by a predetermined logical operation targeted for a specific partial bit in address bits of the selected block address when the defective block is contained in the memory plane. A bit line connected to the selected memory cell selected by the selected block address and a bit line in the dummy block are connected to differential input terminals of a sense amplifier circuit 9.

摘要翻译： 根据本发明的半导体存储装置包括一个或多个包括多个存储器块9的存储器平面8和一个块选择电路，用于解码用于从存储器平面8中选择存储器块9的块地址信号，以选择存储器 块，产生一个虚拟块地址，用于当所选择的块地址的地址位中的特定部分位的目标地址为预定逻辑运算时，选择不同于所选择的块地址的虚拟块和缺陷块的缺陷块地址， 缺陷块包含在存储器平面中。 连接到由选择的块地址选择的所选存储单元的位线和伪块中的位线连接到读出放大器电路9的差分输入端。

公开(公告)号：US07088626B2

公开(公告)日：2006-08-08

申请号：US11055641

申请日：2005-02-09

申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

IPC分类号： G11C7/00

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/063

摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。