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公开(公告)号：US5536674A
公开(公告)日：1996-07-16
申请号：US345891
申请日：1994-11-28
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11
摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.
摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。
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公开(公告)号：US5739564A
公开(公告)日：1998-04-14
申请号：US460605
申请日：1995-06-01
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/265 , H01L21/70
CPC分类号： H01L27/11
摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.
摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。
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3.发明授权Vertical field-effect transistor and a semiconductor memory cell having the transistor 失效垂直场效应晶体管和具有晶体管的半导体存储单元
公开(公告)号：US5416736A
公开(公告)日：1995-05-16
申请号：US279963
申请日：1994-07-25
申请人： Yasunobu Kosa , Howard C. Kirsch
发明人： Yasunobu Kosa , Howard C. Kirsch
IPC分类号： H01L27/10 , H01L21/265 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L21/70 , H01L27/00
CPC分类号： H01L29/66666 , H01L21/26586 , H01L27/11 , H01L27/1108 , H01L29/6675 , H01L29/7827 , H01L29/7834 , Y10S257/904
摘要： The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).
摘要翻译： 本公开包括具有横向凹陷沟道区域（92）的垂直场效应晶体管（115），具有渐变扩散结（31）的垂直场效应晶体管（116），具有梯度扩散结（31）的静态随机存取存储单元（110） 垂直n沟道场效应晶体管（116）和垂直p沟道场效应晶体管（115）及其形成方法。 在一个实施例中，六晶体管静态随机存取存储单元（110）具有平面n沟道场效应晶体管的两个通过晶体管（111和114），两个垂直n的晶体管（113和116） 具有分级扩散结（31）的漏极区的沟道场效应晶体管和具有侧向凹陷沟道区（92）的垂直p沟道薄膜场效应晶体管的两个负载晶体管（112和115）。
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4.发明授权Methods of forming a vertical field-effect transistor and a semiconductor memory cell 失效形成垂直场效应晶体管和半导体存储单元的方法
公开(公告)号：US5364810A
公开(公告)日：1994-11-15
申请号：US921039
申请日：1992-07-28
申请人： Yasunobu Kosa , Howard C. Kirsch
发明人： Yasunobu Kosa , Howard C. Kirsch
IPC分类号： H01L27/10 , H01L21/265 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L21/70 , H01L27/00
CPC分类号： H01L29/66666 , H01L21/26586 , H01L27/11 , H01L27/1108 , H01L29/6675 , H01L29/7827 , H01L29/7834 , Y10S257/904
摘要： The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).
摘要翻译： 本公开包括具有横向凹陷沟道区域（92）的垂直场效应晶体管（115），具有渐变扩散结（31）的垂直场效应晶体管（116），具有梯度扩散结（31）的静态随机存取存储单元（110） 垂直n沟道场效应晶体管（116）和垂直p沟道场效应晶体管（115）及其形成方法。 在一个实施例中，六晶体管静态随机存取存储单元（110）具有平面n沟道场效应晶体管的两个通过晶体管（111和114），两个垂直n的晶体管（113和116） 具有分级扩散结（31）的漏极区的沟道场效应晶体管和具有侧向凹陷沟道区（92）的垂直p沟道薄膜场效应晶体管的两个负载晶体管（112和115）。
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5.发明申请公开(公告)号：US20120126885A1
公开(公告)日：2012-05-24
申请号：US12950797
申请日：2010-11-19
申请人： Werner Juengling , Howard C. Kirsch
发明人： Werner Juengling , Howard C. Kirsch
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/0847 , H01L29/1037 , H01L29/4236 , H01L29/66484 , H01L29/66787 , H01L29/7855
摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
摘要翻译： 提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。 该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。 还包括制造和操作设备的方法。 一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。
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公开(公告)号：US20090237996A1
公开(公告)日：2009-09-24
申请号：US12052300
申请日：2008-03-20
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分 行的存储单元。
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7.发明申请Devices and methods for a threshold voltage difference compensated sense amplifier 有权阈值电压差补偿读出放大器的器件和方法公开(公告)号：US20090129188A1
公开(公告)日：2009-05-21
申请号：US11986333
申请日：2007-11-20
申请人： Tae Kim , Howard C. Kirsch
发明人： Tae Kim , Howard C. Kirsch
IPC分类号： G11C7/08
摘要： Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.
摘要翻译： 针对电压补偿的读出放大器描述实施例。 一个这样的感测放大器包括分别耦合到一对晶体管的一对数字线节点。 第一对开关适于将晶体管的栅极交叉耦合到相应的数字线节点，并且第二对开关适于将晶体管的栅极耦合到电压源。 第一和第二对开关耦合到晶体管的相应栅极，独立于一对晶体管分别耦合到数字线节点。
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公开(公告)号：US20080176378A1
公开(公告)日：2008-07-24
申请号：US12057643
申请日：2008-03-28
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US07365384B2
公开(公告)日：2008-04-29
申请号：US11588748
申请日：2006-10-27
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译： 存储器件包括大致平行于并沿着有源区域的相关带形成的隔离沟槽。 导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。 位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。
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公开(公告)号：US07254074B2
公开(公告)日：2007-08-07
申请号：US11074518
申请日：2005-03-07
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
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