公开(公告)号：US5048101A

公开(公告)日：1991-09-10

申请号：US411268

申请日：1989-09-25

申请人： Yasuo Kurosu ,  Koichi Okazawa ,  Yoshihiro Yokoyama ,  Hiroaki Aotsu ,  Hidefumi Masuzaki

发明人： Yasuo Kurosu ,  Koichi Okazawa ,  Yoshihiro Yokoyama ,  Hiroaki Aotsu ,  Hidefumi Masuzaki

IPC分类号： G06F17/30 ,  G06T1/00 ,  H04N1/00 ,  H04N1/21 ,  H04N1/387

CPC分类号： H04N1/3871 ,  H04N1/00204 ,  H04N1/00283 ,  H04N1/217 ,  H04N2201/0067

摘要： An electronic filing device, comprising an electronic computer such as a personal computer and an image processing device, in which the electronic computer is provided with a data port and a video port and controls the image processing device by using commands and data given to the image processing device by the electronic computer through the data port and image information outputted by the electronic computer through the video port is enlarged within the image processing device, synthesized with image data searched by the image processing device, and displayed on a display device in the image processing device.

摘要翻译： 一种电子归档装置，包括电子计算机，例如个人计算机和图像处理装置，其中电子计算机设置有数据端口和视频端口，并通过使用给图像的命令和数据来控制图像处理装置 由电子计算机通过数据端口处理设备，并且通过视频端口由电子计算机输出的图像信息在图像处理设备内被放大，与由图像处理设备搜索的图像数据合成并显示在图像中的显示设备上 处理装置。

公开(公告)号：US5034733A

公开(公告)日：1991-07-23

申请号：US271275

申请日：1988-11-15

申请人： Koichi Okazawa ,  Yasuo Kurosu ,  Yoshihiro Yokoyama ,  Nobuaki Izuno ,  Tamon Masimo

发明人： Koichi Okazawa ,  Yasuo Kurosu ,  Yoshihiro Yokoyama ,  Nobuaki Izuno ,  Tamon Masimo

IPC分类号： G09G5/00 ,  G06T3/60 ,  G09G1/00 ,  G09G5/32 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395

CPC分类号： G09G5/363 ,  G06T3/606 ,  G09G1/00 ,  G09G5/39 ,  G09G2340/0492

摘要： An image data rotating apparatus has an n.times.n dot matrix memory which temporarily stores n.times.n dots of image data supplied from a first image data memory. A row/column selector selects one row or column of the n.times.n dot matrix memory in response to a rotation indicating signal, which selects an integer times 90.degree. as a rotating degree, for example, 0.degree., 90.degree., 180.degree., 270.degree. or the like. The n dots of image data stored in the selected row or colum are re-written by outputting the stored data into a second image data memory, and by inputting another n dots of image data from the first image data memory in the same cycle, and with the repeating of this cycle, all the n.times.n dots of image data stored in the n.times.n dot matrix memory are re-written so that the rotated image data can be retrieved from the second image data memory.

摘要翻译： 图像数据旋转装置具有n×n点阵存储器，其临时存储从第一图像数据存储器提供的图像数据的n×n个点。 行/列选择器响应于旋转指示信号选择nxn点矩阵存储器的一行或一列，其选择整数倍90度作为旋转度，例如0°，90°，180°，270° 或类似物。 通过将存储的数据输出到第二图像数据存储器中，并且通过在同一周期中从第一图像数据存储器输入另外的n个点的图像数据来重新写入存储在选择的行或列中的图像数据的n个点，以及 随着该循环的重复，存储在nxn点阵存储器中的图像数据的所有n×n个点被重新写入，从而可以从第二图像数据存储器检索旋转的图像数据。

公开(公告)号：US4943857A

公开(公告)日：1990-07-24

申请号：US184394

申请日：1988-04-21

申请人： Nobuaki Izuno ,  Yasuo Kurosu ,  Koichi Okazawa ,  Yoshihiro Yokoyama ,  Kensuke Ooyu

发明人： Nobuaki Izuno ,  Yasuo Kurosu ,  Koichi Okazawa ,  Yoshihiro Yokoyama ,  Kensuke Ooyu

IPC分类号： H03L7/081 ,  H04N5/04

CPC分类号： H04N5/04 ,  H03L7/0814

摘要： A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.

摘要翻译： 从工作站提供的视频信号和水平同步信号由具有不同延迟量的多个延迟电路延迟，并且检测采样时钟信号和延迟信号之间的相位差。 时钟发生器产生具有相反相位和相同频率的两种时钟脉冲。 时钟选择器响应于相位差选择时钟脉冲之一作为采样脉冲信号。 此外，检测水平同步信号和视频信号之间的相位差，使得水平同步信号和视频信号之间的相位差保持恒定。

公开(公告)号：US5276818A

公开(公告)日：1994-01-04

申请号：US512810

申请日：1990-04-20

申请人： Koichi Okazawa ,  Hiroaki Aotsu ,  Hitoshi Kawaguchi ,  Masami Jikihara ,  Kazushi Kobayashi ,  Koichi Kimura ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Hiroaki Aotsu ,  Hitoshi Kawaguchi ,  Masami Jikihara ,  Kazushi Kobayashi ,  Koichi Kimura ,  Tetsuya Mochida

IPC分类号： G06F13/28 ,  G06F13/36 ,  G06F13/364 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217 ,  G06F13/364

摘要： A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.

摘要翻译： 一种用于信息处理系统的总线系统，其中在公共总线上控制多个模块之间的数据传输。 响应于来自模块的总线使用请求，发出用于中止由具有较低优先级的另一模块执行的数据传输的命令。 正在传送数据的模块通过发出一个指示要传送的字是最终字的信号来响应中止命令。 通过与从总线控制器提供的时钟同步的与数据具有相同宽度的地址总线，在主机和从机之间传送数据。

公开(公告)号：US07802045B2

公开(公告)日：2010-09-21

申请号：US12501684

申请日：2009-07-13

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

公开(公告)号：US07711817B2

公开(公告)日：2010-05-04

申请号：US12243081

申请日：2008-10-01

申请人： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

发明人： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

IPC分类号： G06F15/173

CPC分类号： G06F9/5055 ,  G06F9/5044 ,  G06F2209/5015 ,  H04L29/12047 ,  H04L41/5009 ,  H04L61/15 ,  H04L67/36

摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

摘要翻译： 在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。 当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息 。 由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。 因此，用户可以更多地直接接收必要的服务。

公开(公告)号：US07577781B2

公开(公告)日：2009-08-18

申请号：US12155047

申请日：2008-05-29

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US07398346B2

公开(公告)日：2008-07-08

申请号：US11543878

申请日：2006-10-06

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

公开(公告)号：US07177970B2

公开(公告)日：2007-02-13

申请号：US10274881

申请日：2002-10-22

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US06425037B1

公开(公告)日：2002-07-23

申请号：US09407064

申请日：1999-09-28

申请人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

发明人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

IPC分类号： G06F1300

CPC分类号： G06F13/364

摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.

摘要翻译： 本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个 连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置 访问目的地是预定模块。 每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态 并决定是否给予巴士总线职业权。