公开(公告)号：US06518559B2

公开(公告)日：2003-02-11

申请号：US09731802

申请日：2000-12-08

申请人： Yasuyuki Endo ,  Yutaka Arima ,  Hiroki Ui

发明人： Yasuyuki Endo ,  Yutaka Arima ,  Hiroki Ui

IPC分类号： H01L2700

CPC分类号： H04N5/374 ,  H04N5/341 ,  H04N5/365

摘要： A semiconductor image pickup device includes a pixel array having pixels arranged in a matrix. Each pixel includes a photodiode that converts an optical signal into an electrical signal, and a transistor connected to a charge accumulation section of the photodiode. A buffer is additionally provided. This buffer controls the transistor of the pixels using a lower control power supply voltage than a power supply voltage of the pixel array.

摘要翻译： 半导体图像拾取装置包括具有排列成矩阵的像素的像素阵列。 每个像素包括将光信号转换成电信号的光电二极管，以及连接到光电二极管的电荷累积部分的晶体管。 另外提供一个缓冲区。 该缓冲器使用比像素阵列的电源电压更低的控制电源电压来控制像素的晶体管。

公开(公告)号：US07098951B2

公开(公告)日：2006-08-29

申请号：US10237736

申请日：2002-09-10

申请人： Yutaka Arima

发明人： Yutaka Arima

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H01L27/14603 ,  H04N5/3559 ,  H04N5/3745

摘要： Each pixel includes first and second photodiodes that are receiving-light detecting elements. The first photodiode applies a first potential according to an amount of light entering into the corresponding pixel. An internal node is electrically coupled with an internal node in another pixel via a resistance component. Hence, the second photodiode applies a second potential according to an average amount of light on the periphery to the corresponding internal node. A pixel signal generating circuit reads out a multiplied result of the first and second potentials as a pixel signal. The pixel signal has an intensity corresponding to the amount of light in the pixel in accordance with a receiving-light sensitivity characteristic (signal amplification factor) that is automatically adjusted based on an average amount of light in a region on the periphery of the pixel.

公开(公告)号：US06774733B2

公开(公告)日：2004-08-10

申请号：US10302880

申请日：2002-11-25

申请人： Yutaka Arima

发明人： Yutaka Arima

IPC分类号： H03B524

CPC分类号： H03K3/0315 ,  H01L27/088 ,  H01L29/0839 ,  H01L29/7832

摘要： A-MOS devices capable of continuously modulating a gain coefficient &bgr; in accordance with a voltage applied to a control gate provided in addition to a normal gate, are connected in an odd number of stages to configure a ring oscillator. An oscillation circuit can be implemented capable of modulating an oscillation frequency in accordance with the control gate's voltage in a wide range.

摘要翻译： 能够根据施加到除常规栅极之外提供的控制栅极的电压连续调制增益系数β的A-MOS器件以奇数个级连接以配置环形振荡器。 可以实现能够在宽范围内根据控制栅极的电压来调制振荡频率的振荡电路。

公开(公告)号：US5764557A

公开(公告)日：1998-06-09

申请号：US580193

申请日：1995-12-28

申请人： Kunihiko Hara ,  Yutaka Arima

发明人： Kunihiko Hara ,  Yutaka Arima

IPC分类号： G06F17/10 ,  G06F7/544 ,  G06T7/60 ,  G06F7/48

CPC分类号： G06F7/5443

摘要： A product-sum calculation apparatus is provided for cumulatively adding up respective products of first input data and second input data. There is further provided a product-sum calculation unit integrated circuit apparatus including the product-sum calculation apparatus, and a cumulative adder. In the product-sum calculation apparatus, a barrel shifter shifts the first input data by a predetermined number of bits based on the second input data, and an adder adds the shifted data outputted from the barrel shifter and inputted through a first input terminal thereof, and data inputted through a second input terminal thereof. A register temporarily stores data outputted from the adder, outputs a stored data to the adder through the second input terminal of the adder, and outputs the stored data through an output terminal. Further, there is provided a multiplexer for selecting either one of third input data inputted through a first input terminal thereof, and data inputted through a second input terminal thereof. Accordingly, the product-sum calculation apparatus calculates a product of the first input data and the second input data, calculates a sum of a calculated product and the third input data, and outputs a calculated sum from the output terminal.

摘要翻译： 提供一种产品和计算装置，用于累积地将第一输入数据和第二输入数据的各个乘积相加。 还提供了一种产品和计算单元集成电路装置，包括乘积和计算装置和累积加法器。 在乘积和计算装置中，桶形移位器基于第二输入数据将第一输入数据移位预定位数，加法器将从桶形移位器输出并经其第一输入端输入的移位数据相加， 以及通过其第二输入端输入的数据。 寄存器临时存储从加法器输出的数据，通过加法器的第二输入端将存储的数据输出到加法器，并通过输出端输出存储的数据。 此外，提供了一种多路复用器，用于选择通过其第一输入端输入的第三输入数据中的一个和通过其第二输入端输入的数据。 因此，积和计算装置计算第一输入数据和第二输入数据的乘积，计算计算乘积和第三输入数据的和，并从输出端输出计算出的和。

公开(公告)号：US06972591B2

公开(公告)日：2005-12-06

申请号：US10404431

申请日：2003-04-02

申请人： Yutaka Arima

发明人： Yutaka Arima

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/173

CPC分类号： H03K19/003 ,  H03K19/01707

摘要： An inverter circuit which is a representative example of the logic circuit includes a p-channel A-MOS transistor and an n-channel transistor. The gain coefficient β of the p-channel A-MOS transistor and n-channel transistor changes according to a voltage on a control gate. The control gate of the p-channel A-MOS transistor and n-channel MOS transistor is connected to an output node of the inverter circuit, and the normal MOS gate is connected to an input node of the inverter circuit. Thus, the ON resistance of the p-channel A-MOS transistor and n-channel transistor is automatically modulated to decrease as the source-drain voltage increases.

摘要翻译： 作为逻辑电路的代表性例子的逆变器电路包括p沟道A-MOS晶体管和n沟道晶体管。 p沟道A-MOS晶体管和n沟道晶体管的增益系数β根据控制栅极上的电压而变化。 p沟道A-MOS晶体管和n沟道MOS晶体管的控制栅极连接到逆变器电路的输出节点，并且正常MOS栅极连接到逆变器电路的输入节点。 因此，随着源极 - 漏极电压的增加，p沟道A-MOS晶体管和n沟道晶体管的导通电阻被自动调制。

公开(公告)号：US5532938A

公开(公告)日：1996-07-02

申请号：US306300

申请日：1994-09-15

申请人： Yoshikazu Kondo ,  Yutaka Arima

发明人： Yoshikazu Kondo ,  Yutaka Arima

IPC分类号： G06F15/18 ,  G06F15/80 ,  G06N3/02 ,  G06N3/063 ,  G06F7/38 ,  G06F7/00

CPC分类号： G06F9/3885 ,  G06F15/8015 ,  G06F9/3887

摘要： Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data input port, a process data output port and an address data output port. Address data appearing on the address ports specify addresses of a local memory. Each of the arithmetic units reads corresponding numeric data from the local memory and executes arithmetic processing in accordance with the instruction supplied from the control unit through a computing element group and a register group. In each arithmetic unit, it is possible to specify addresses of the local memory independently of each other. Each unit include circuitry for omitting an arithmetic operation on data read from the local memory when the read out data is negligible.

摘要翻译： 通过指令广播总线向算术单元提供来自控制单元的指令。 每个算术单元包括处理数据输入端口，地址数据输入端口，处理数据输出端口和地址数据输出端口。 出现在地址端口的地址数据指定本地存储器的地址。 每个算术单元从本地存储器读取对应的数字数据，并根据从控制单元通过计算单元组和寄存器组提供的指令执行算术处理。 在每个算术单元中，可以独立于彼此指定本地存储器的地址。 每个单元包括当读出数据可忽略时省略从本地存储器读取的数据的算术运算的电路。

公开(公告)号：US5148514A

公开(公告)日：1992-09-15

申请号：US515476

申请日：1990-04-24

申请人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

发明人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

IPC分类号： G06N3/063

CPC分类号： G06N3/063

摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.

摘要翻译： 具有Boltzmann模型学习功能的延伸定向集成电路装置包括多个突触，其表示以矩阵排列的单元，以形成包括半导体芯片上的第一和第二三角形的矩形，多个神经元表示单元和多个 沿矩形的第一和第二侧布置的教育者信号控制电路以及沿矩形的第三和第四侧布置的多个缓冲电路。 第一面与第三面相反，第二面与第四面相反。 轴突信号传输线和枝晶信号线被布置成使得表示单元的神经元在第二直角三角形的第一直角三角形的每一个中是全连接的。 或者，轴突信号线和枝晶信号与突触表示单位矩阵的行和列平行布置，使得表示单元的神经元表示在矩形中。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。

公开(公告)号：US07187016B2

公开(公告)日：2007-03-06

申请号：US10221137

申请日：2002-01-22

申请人： Yutaka Arima

发明人： Yutaka Arima

IPC分类号： H01L29/76

CPC分类号： H01L29/4238 ,  H01L29/7831

摘要： In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelogram, and a second gate forming a channel region substantially containing a triangle between the channel region formed by the first gate and each of a source region and a drain region. In some embodiments, there is included a channel region formed by the first gate that is sandwiched by the channel region formed by the second gate, all the channel regions together substantially forming a rectangle or a parallelogram. As such, a semiconductor device allowing a gain coefficient β of an MOS transistor to be modulated by voltage in an analog manner can readily be produced by conventional processing technology and incorporated into any conventional LSIs configured by a CMOS circuit.

摘要翻译： 在半导体器件中，相对于栅极或者调整晶体管的增益系数的沟道的方向或角度来控制电场。 在一些实施例中，提供了形成矩形或平行四边形中的沟道区的第一栅极，以及形成基本上包含由第一栅极形成的沟道区与源区和 漏区。 在一些实施例中，包括由第一栅极形成的沟道区，该沟道区被由第二栅极形成的沟道区夹在中间，所有沟道区基本上形成矩形或平行四边形。 因此，通过常规的处理技术可以容易地通过以模拟方式通过电压调制MOS晶体管的增益系数β的半导体器件，并且并入由CMOS电路配置的任何常规LSI中。

公开(公告)号：US5696883A

公开(公告)日：1997-12-09

申请号：US971038

申请日：1992-11-03

申请人： Yutaka Arima

发明人： Yutaka Arima

IPC分类号： G06F15/18 ,  G06G7/60 ,  G06J1/00 ,  G06N3/06 ,  G06N3/063 ,  G06N99/00 ,  G06F7/00

CPC分类号： G06J1/00 ,  G06N3/063 ,  G06N3/0635

摘要： A self-organizable neural network expressing unit includes a plurality of neuron units electronically expressing nerve cell bodies, and a plurality of synapse expressing units electronically expressing synapses for coupling neuron units through programmed coupling strengths represented by synapse load values, and a control circuit for supplying a pattern of random number data as an educator data. When the pattern of random number data is generated, the neural network expressing unit carries out correction of synapse load values as in a learning mode of operation using the pattern of random number data as an educator data. The memorized internal states in the neural network expressing unit is reinforced based on a faded memory thereof, and the synapse load values are precisely maintained for a long time, resulting in a reliable neural network expressing unit.

摘要翻译： 自组织神经网络表达单元包括电子表达神经细胞体的多个神经元单元，以及电子表达突触的多个突触表达单元，用于通过由突触载荷值表示的编程耦合强度来耦合神经元单元;以及控制电路， 作为教育者数据的随机数字数据模式。 当产生随机数字数据的模式时，神经网络表示单元使用随机数数据的模式作为教育者数据来执行在学习操作模式中的突触负载值的校正。 神经网络表达单元中存储的内部状态基于其褪色存储器被加强，并且突触负载值被精确地保持很长时间，从而产生可靠的神经网络表达单元。

公开(公告)号：US5293457A

公开(公告)日：1994-03-08

申请号：US877514

申请日：1992-05-01

申请人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

发明人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/063 ,  G06N99/00 ,  H01L21/822 ,  H01L27/04 ,  G06F7/00

CPC分类号： G06N3/063

摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.Si from the synapse load Wij and the first axon signal Si and transfers the same to a first dendrite signal line, and a second product signal indicating a product Wij.multidot.Sj from the synapse load Wij and the second axon signal Sj and transfers the same onto a second dendrite signal line.

摘要翻译： 具有Boltzmann模型学习功能的延伸定向集成电路器件包括表示以矩阵排列的单元的多个突触，多个神经元表示单元，多个教育者信号控制电路和多个缓冲电路。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。 每个突触表示单元包括学习控制电路，该学习控制电路响应于第一轴突信号Si和第二轴突信号Sj，根据预定的学习规则导出突触负荷变化值数据，突变负载表示电路响应于 突触负荷改变数值数据并保持校正的突触负载值Wij，第一突触耦合操作电路从突触负载Wij和第一轴突信号Si导出指示产品Wij * Si的电流信号，并将其转移到第一 枝晶信号线和第二产品信号，其从突触载荷Wij和第二轴突信号Sj指示乘积Wij * Sj，并将其传送到第二枝晶信号线。