公开(公告)号：US07316954B2

公开(公告)日：2008-01-08

申请号：US10968233

申请日：2004-10-19

申请人： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

发明人： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.

摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该器件还包括在接触孔中延伸并且电连接到第一导电类型的半导体区域的第一导电类型的多晶Si-1-x-Ge 提供导电类型。 还提供了制造集成电路器件的相关方法。

公开(公告)号：US20050087828A1

公开(公告)日：2005-04-28

申请号：US10990429

申请日：2004-11-18

申请人： Yeong-kwan Kim ,  Dong-chan Kim ,  Seung-hwan Lee ,  Young-wook Park

发明人： Yeong-kwan Kim ,  Dong-chan Kim ,  Seung-hwan Lee ,  Young-wook Park

IPC分类号： H01L21/20 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/76 ,  H01L31/115

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/10885

摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

摘要翻译： 具有通过原子层沉积形成的薄膜的半导体器件及其制造方法，其中所述半导体器件包括形成在沟槽的内壁和底部上的衬垫层，形成在栅堆叠图案功能的侧壁上的栅极间隔 作为栅极线，形成在栅极间隔物和栅极堆叠图案上的第一防止气泡层，形成在用作位线的位线堆叠图案的侧壁上的位线间隔物和形成在位线上的第二防止气泡层 间隔物和栅极堆叠图案，并且上述中的至少一个由氮化硅层和氧化硅层的多层或氧化硅层和氮化硅层的多层形成，从而填充 沟槽，栅极堆叠图案或无空隙的位线堆叠图案。

公开(公告)号：US07544607B2

公开(公告)日：2009-06-09

申请号：US10990429

申请日：2004-11-18

申请人： Yeong-kwan Kim ,  Dong-chan Kim ,  Seung-hwan Lee ,  Young-wook Park

发明人： Yeong-kwan Kim ,  Dong-chan Kim ,  Seung-hwan Lee ,  Young-wook Park

IPC分类号： H01L21/4763 ,  H01L29/00 ,  H01L23/58

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/10885

摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

公开(公告)号：US06833310B2

公开(公告)日：2004-12-21

申请号：US09902607

申请日：2001-07-12

申请人： Yeong-kwan Kim ,  Dong-chan Kim ,  Seung-hwan Lee ,  Young-wook Park

发明人： Yeong-kwan Kim ,  Dong-chan Kim ,  Seung-hwan Lee ,  Young-wook Park

IPC分类号： H01L2176

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/10885

摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

摘要翻译： 具有通过原子层沉积形成的薄膜的半导体器件及其制造方法，其中所述半导体器件包括形成在沟槽的内壁和底部上的衬垫层，形成在栅堆叠图案功能的侧壁上的栅极间隔 作为栅极线，形成在栅极间隔物和栅极堆叠图案上的第一防止气泡层，形成在用作位线的位线堆叠图案的侧壁上的位线间隔物和形成在位线上的第二防止气泡层 间隔物和栅极堆叠图案，并且上述中的至少一个由氮化硅层和氧化硅层的多层或氧化硅层和氮化硅层的多层形成，从而填充 沟槽，栅极堆叠图案或无空隙的位线堆叠图案。

公开(公告)号：US20050064660A1

公开(公告)日：2005-03-24

申请号：US10968233

申请日：2004-10-19

申请人： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

发明人： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

IPC分类号： H01L21/283 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.

摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。 还提供了制造集成电路器件的相关方法。

公开(公告)号：US06828616B2

公开(公告)日：2004-12-07

申请号：US10012116

申请日：2001-11-13

申请人： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

发明人： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1−xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.

摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有与衬底表面相邻的第一导电类型的半导体区域。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。

公开(公告)号：US06468924B2

公开(公告)日：2002-10-22

申请号：US09871430

申请日：2001-05-31

申请人： Seung-hwan Lee ,  Yeong-kwan Kim ,  Dong-chan Kim ,  Young-wook Park

发明人： Seung-hwan Lee ,  Yeong-kwan Kim ,  Dong-chan Kim ,  Young-wook Park

IPC分类号： H01L2131

CPC分类号： H01L21/0228 ,  C23C16/34 ,  C23C16/345 ,  C23C16/402 ,  C23C16/403 ,  C23C16/405 ,  C23C16/409 ,  C23C16/45531 ,  C23C16/45542 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/02274 ,  H01L21/3185

摘要： Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.

公开(公告)号：US6077573A

公开(公告)日：2000-06-20

申请号：US83350

申请日：1998-05-22

申请人： Young-sun Kim ,  Sang-hyeop Lee ,  Seung-hwan Lee ,  Young-wook Park ,  Mikio Takagi

发明人： Young-sun Kim ,  Sang-hyeop Lee ,  Seung-hwan Lee ,  Young-wook Park ,  Mikio Takagi

IPC分类号： H01L27/04 ,  C23C16/24 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H05H1/24

CPC分类号： C23C16/24

摘要： A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.

摘要翻译： 形成微电子器件的方法包括使用等离子体增强化学气相沉积在微电子衬底上形成掺杂杂质的非晶硅层的步骤。 图案化杂质掺杂非晶硅层，使得微电子衬底的部分暴露在图案化的非晶硅层附近。 然后在图案化的非晶硅层上形成半球形的硅层。 此外，形成杂质掺杂非晶硅层的步骤可以在400℃以下的温度下进行。

公开(公告)号：US20080246092A1

公开(公告)日：2008-10-09

申请号：US12072445

申请日：2008-02-26

申请人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-Min Choi

发明人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-Min Choi

IPC分类号： H01L29/00 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

摘要翻译： 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。

公开(公告)号：US07144771B2

公开(公告)日：2006-12-05

申请号：US10616056

申请日：2003-07-09

申请人： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

发明人： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

IPC分类号： H01L21/8242

CPC分类号： H01L21/02186 ,  C23C16/405 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

摘要翻译： 形成电子器件的方法包括提供第一电极，在第一电极上提供电介质氧化物层，并在电介质氧化物层上提供第二电极，使得电介质氧化物层位于第一和第二电极之间。 更具体地，与第一电极相邻的电介质氧化物层的第一部分可以具有第一密度的钛，并且与第一电极相对的电介质氧化物层的第二部分可具有不同于第一密度的钛的第二密度。 还讨论了相关结构。