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    Asymmetric memory cell
    2.
    发明申请
    Asymmetric memory cell 有权
    不对称记忆单元

    公开(公告)号：US20050145886A1

    公开(公告)日：2005-07-07

    申请号：US10750572

    申请日：2003-12-31

    申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

    发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

    IPC分类号： G11C11/404 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

    摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

    摘要翻译： 一些实施例提供了包括体区，源区和漏区的存储单元。 主体区域掺杂有第一类型的电荷载流子，源极区域设置在体区中并掺杂有第二类型的电荷载流子，并且漏极区域设置在体区中并掺杂有第二类型的载流子 类型。 主体区域和源极区域形成第一结，主体区域和漏极区域形成第二结，并且在第一接合点不偏向的情况下，从体区域到源极区域的第一结的导电率基本上 在第二接头不偏差的情况下，小于从体区到漏区的第二结的导电性。

    Memory cell without halo implant
    5.
    发明申请
    Memory cell without halo implant 有权
    无光晕植入的记忆细胞

    公开(公告)号：US20060054971A1

    公开(公告)日：2006-03-16

    申请号：US11268430

    申请日：2005-11-07

    申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

    发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

    IPC分类号： H01L29/76

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

    摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

    摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

    BITE-LINE DROOP REDUCTION
    8.
    发明申请
    BITE-LINE DROOP REDUCTION 失效
    BINE-LINE DROOP减少

    公开(公告)号：US20050146956A1

    公开(公告)日：2005-07-07

    申请号：US10746148

    申请日：2003-12-24

    申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

    发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

    IPC分类号： G11C7/00 ,  G11C7/12

    CPC分类号： G11C7/12

    摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

    摘要翻译： 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。