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1.发明授权Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter 失效信号处理装置，信号处理方法，Δ-Σ调制型小数分频PLL频率合成器，无线电通信装置，Δ-Σ调制型D / A转换器公开(公告)号：US06917317B2
公开(公告)日：2005-07-12
申请号：US10495863
申请日：2003-08-27
申请人： Yoichi Nagaso , Takaharu Saeki
发明人： Yoichi Nagaso , Takaharu Saeki
IPC分类号： H03M1/20 , H03L7/183 , H03L7/197 , H03M1/08 , H03M3/00 , H03M3/02 , H03M7/00 , H03M7/36 , H04B14/06
CPC分类号： H03M7/3008 , H03L7/1978 , H03M7/3042
摘要： A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n−1).
摘要翻译： 分数分频器（28）包括用于保持分频数据的锁存器（31），DeltaSigma调制器（33），数字抖动电路（32），用于从锁存器接收代表分频数据的分数部分的数字输入F （31），并且向Delta-Σ调制器（33）提供在F + k和Fk（其中k是整数）或F值本身之间交替变化的数字输出，以及用于执行基于分数分频的电路装置（34至38） 分频数据的整数部分（M值）和Delta-Σ调制器（33）的输出。 数字抖动电路（32）可用于抑制当DeltaSigma调制器（33）接收到特定的F值（例如，F = 2-N）时由于特定频率的量化噪声的集中而产生的寄生信号 1 ）。
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2.发明申请Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter 失效信号处理装置，信号处理方法，Δ-Σ调制方式小数分频器频率合成器，无线电通信装置，Δ-Σ调制型d / a转换器公开(公告)号：US20050017887A1
公开(公告)日：2005-01-27
申请号：US10495863
申请日：2003-08-27
申请人： Yoichi Nagaso , Takaharu Saeki
发明人： Yoichi Nagaso , Takaharu Saeki
IPC分类号： H03M1/20 , H03L7/183 , H03L7/197 , H03M1/08 , H03M3/00 , H03M3/02 , H03M7/00 , H03M7/36 , H04B14/06
CPC分类号： H03M7/3008 , H03L7/1978 , H03M7/3042
摘要： A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n−1).
摘要翻译： 分数分频器（28）包括用于保持分频数据的锁存器（31），DeltaSigma调制器（33），数字抖动电路（32），用于从锁存器接收代表分频数据的分数部分的数字输入F （31），并且向Delta-Σ调制器（33）提供在F + k和Fk（其中k是整数）或F值本身之间交替变化的数字输出，以及用于执行基于分数分频的电路装置（34至38） 分频数据的整数部分（M值）和Delta-Σ调制器（33）的输出。 数字抖动电路（32）可用于抑制当DeltaSigma调制器（33）接收到特定的F值（例如，F = 2
）时由于特定频率处的量化噪声的集中而产生的寄生信号 ）。
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