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    SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME 有权
    含有碳化硅层的硅碳化硅半导体器件及其制造方法

    公开(公告)号：US20090250705A1

    公开(公告)日：2009-10-08

    申请号：US12267040

    申请日：2008-11-07

    申请人： Tomokatsu WATANABE ,  Sunao Aya ,  Naruhisa Miura ,  Keiko Sakai ,  Shohei Yoshida ,  Toshikazu Tanioka ,  Yukiyasu Nakao ,  Yoichiro Tarui ,  Masayuki Imaizumi

    发明人： Tomokatsu WATANABE ,  Sunao Aya ,  Naruhisa Miura ,  Keiko Sakai ,  Shohei Yoshida ,  Toshikazu Tanioka ,  Yukiyasu Nakao ,  Yoichiro Tarui ,  Masayuki Imaizumi

    IPC分类号： H01L29/24 ,  H01L21/34

    CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

    摘要： A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C. becomes lower than that in a case where the p++ region is formed by ion implantation at a temperature over 300° C. Further, this can avoid any process failure.

    摘要翻译： 碳化硅半导体器件的p基极欧姆接触由通过高浓度离子注入形成的p ++层和金属电极组成。 由于在室温下进行的高浓度离子注入使p ++层的晶体显着降低，导致处理失败，所以使用在高温下注入的方法。 在器件的开关损耗等方面，期望p基极欧姆接触的电阻率应该更低。 在众所周知的技术中，在离子注入温度，欧姆接触电阻率和工艺故障之间的详细关系中没有提及。 然后，在离子注入步骤中，碳化硅晶片的温度保持在175℃至300℃的范围内，更优选在175℃至200℃的范围内。 在175℃〜300℃的温度范围内通过离子注入形成的p ++区域的p基极欧姆接触变得低于在超过300°的温度下通过离子注入形成p ++区域的情况下的p基极欧姆接触 此外，这可以避免任何过程失败。

    Semiconductor device having junction termination extension
    7.
    发明授权
    Semiconductor device having junction termination extension 有权
    具有连接终端延伸的半导体器件

    公开(公告)号：US07564072B2

    公开(公告)日：2009-07-21

    申请号：US11142322

    申请日：2005-06-02

    申请人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

    发明人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

    IPC分类号： H01L29/74

    CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/872 ,  Y10S388/917

    摘要： A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 μm or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm−2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm−2.

    摘要翻译： 半导体器件包括与形成在SiC衬底中的n型漂移层肖特基接触的阳极电极和形成在阳极电极外部的JTE区域。 JTE区域由在阳极电极的边缘的漂移层的上部形成的第一p型区域和形成在具有较低表面杂质浓度的第一p型区域外的第二p型区域构成 比第一个p型区域。 第二个p型区域距离阳极电极的边缘向外提供15个或更多个外部。 第一p型区域的表面杂质浓度范围为1.8×1013〜4×1013cm-2，第二p型区域的表面杂质浓度为1×10 13〜2.5×10 13 cm -2。

    Semiconductor device
    8.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060118812A1

    公开(公告)日：2006-06-08

    申请号：US11142322

    申请日：2005-06-02

    申请人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

    发明人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

    IPC分类号： H01L29/74

    CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/872 ,  Y10S388/917

    摘要： A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 μm or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm−2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm−2.

    摘要翻译： 半导体器件包括与形成在SiC衬底中的n型漂移层肖特基接触的阳极电极和形成在阳极电极外部的JTE区域。 JTE区域由在阳极电极的边缘的漂移层的上部形成的第一p型区域和形成在具有较低表面杂质浓度的第一p型区域外的第二p型区域构成 比第一个p型区域。 第二个p型区域距离阳极电极的边缘向外提供15个或更多个外部。 第一p型区域的表面杂质浓度范围为1.8×10 13〜4×10 -3 cm -2，而第二p型区域的表面杂质浓度为 型区域范围为1×10 13至2.5×10 13 cm -2。

    Method of manufacturing a SiC vertical MOSFET
    9.
    发明授权
    Method of manufacturing a SiC vertical MOSFET 有权
    制造SiC垂直MOSFET的方法

    公开(公告)号：US07285465B2

    公开(公告)日：2007-10-23

    申请号：US11353992

    申请日：2006-02-15

    申请人： Yoichiro Tarui ,  Ken-ichi Ohtsuka ,  Masayuki Imaizumi ,  Hiroshi Sugimoto ,  Tetsuya Takami

    发明人： Yoichiro Tarui ,  Ken-ichi Ohtsuka ,  Masayuki Imaizumi ,  Hiroshi Sugimoto ,  Tetsuya Takami

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

    摘要： A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.

    摘要翻译： 提供了一种半导体器件及其制造方法，其中改善了沟道电阻和JFET电阻之间的折衷关系，从而改善了器件的小型化，并且通过离子注入使用相同的掩模形成源极区域和基极区域。 在使用SiC的垂直MOSFET中，通过使用相同的锥形掩模的离子注入形成源极区域和基极区域，以使基极区域呈锥形。 当锥形掩模的材料与离子注入中的SiC具有相同的范围时，锥形掩模的锥角设定为30°至60°，当锥形掩模的材料为SiO 2 。

    Manufacturing method of silicon carbide semiconductor device
    10.
    发明授权
    Manufacturing method of silicon carbide semiconductor device 有权
    碳化硅半导体器件的制造方法

    公开(公告)号：US08685848B2

    公开(公告)日：2014-04-01

    申请号：US13355710

    申请日：2012-01-23

    申请人： Yoshinori Matsuno ,  Yoichiro Tarui

    发明人： Yoshinori Matsuno ,  Yoichiro Tarui

    IPC分类号： H01L21/329

    CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6606 ,  H01L29/872

    摘要： A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.

    摘要翻译： 通过干热氧化在外延层上形成氧化硅膜，在SiC衬底的背面上形成欧姆电极，在SiC衬底的欧姆电极和背面之间形成欧姆接头，退火SiC 衬底，除去氧化硅膜，在外延层上形成肖特基电极。 然后，进行烧结处理以在肖特基电极和外延层之间形成肖特基结。