公开(公告)号：US07884875B2

公开(公告)日：2011-02-08

申请号：US11866940

申请日：2007-10-03

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H04N5/225 ,  H01L21/00

CPC classification number: H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.

Abstract translation: 提供了一种相机模块及其制造方法。 该方法包括制备包括上连接部分的透镜结构。 下连接部分形成在基板的预定区域中。 下连接部分分别限定芯片区域并配合在上连接部分中。 图像传感器芯片位于芯片区域的底表面上。 透镜结构使用上连接部分和下连接部分粘合到基板上。

公开(公告)号：US20080157394A1

公开(公告)日：2008-07-03

申请号：US12003544

申请日：2007-12-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3121 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2224/03

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

Abstract translation: 半导体封装可以包括半导体图案，接合焊盘和聚合物绝缘构件。 半导体图案可以包括半导体器件和第一孔。 接合焊盘可以包括布线​​图案和插头。 布线图案可以形成在半导体图案的上表面上。 插头可以从布线图案延伸以填充第一孔。 聚合物绝缘构件可以形成在半导体图案的下表面上，并且可以包括暴露插头的下端的第二孔。 制造半导体封装的方法可以包括通过半导体衬底形成第一孔; 形成焊盘和插头; 将支撑构件附接到所述基板的上表面; 减小基板的厚度; 在所述基板的下表面上形成聚合物绝缘部件; 并切割基板。

公开(公告)号：US07939947B2

公开(公告)日：2011-05-10

申请号：US12769232

申请日：2010-04-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract translation: 公开了半导体封装结构。 半导体封装结构包括半导体衬底上的半导体芯片。 每个半导体芯片包括芯片焊盘。 贯通孔延伸穿过每个半导体芯片。 再分配结构和芯片选择互连线设置在每个半导体芯片上。 再分配结构将至少一个通孔与至少一个芯片焊盘电连接。 每个芯片选择互连线包括连接到对应数量的通孔的第一区域和将至少一个第一区域与其中一个芯片焊盘连接的第二区域。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US20110014748A1

公开(公告)日：2011-01-20

申请号：US12923554

申请日：2010-09-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L21/50 ,  H01L21/302

CPC classification number: H01L23/3121 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2224/03

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

公开(公告)号：US20080150089A1

公开(公告)日：2008-06-26

申请号：US11979562

申请日：2007-11-06

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在晶片上形成绝缘层。 晶片可以具有彼此面对的有源表面和非活性表面，并且绝缘层可以形成在有源表面上。 可以在绝缘层上形成焊盘，并且可以在绝缘层中形成第一孔。 然后可以在第一孔的内壁上形成第一孔绝缘层。 可以在第一孔下方形成第二孔。 第二孔可以形成为从第一孔延伸到晶片。 第二孔绝缘层可以形成在第二孔的内壁上。 还可以提供根据该方法制造的半导体器件。

公开(公告)号：US20100207278A1

公开(公告)日：2010-08-19

申请号：US12769232

申请日：2010-04-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract translation: 公开了半导体封装结构。 半导体封装结构包括半导体衬底上的半导体芯片。 每个半导体芯片包括芯片焊盘。 贯通孔延伸穿过每个半导体芯片。 再分配结构和芯片选择互连线设置在每个半导体芯片上。 再分配结构将至少一个通孔与至少一个芯片焊盘电连接。 每个芯片选择互连线包括连接到对应数量的通孔的第一区域和将至少一个第一区域与其中一个芯片焊盘连接的第二区域。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US20070045836A1

公开(公告)日：2007-03-01

申请号：US11436822

申请日：2006-05-18

Applicant: Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-Il Han ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-Il Han ,  Dong-Ho Lee

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

Abstract: In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.

Abstract translation: 在堆叠式芯片结构及其制造方法中，使用消除下部和上部芯片之间的空隙以及与空隙相关的开裂和分层问题的相对简单的工艺，完全填充下部芯片和上部芯片之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供间隙的完全填充的同时，大大提高了芯片/晶片之间的粘附。 另外，提高了机械可靠性，降低了CTE失配，缓解了翘曲，开裂，脱层等问题，提高了设备​​的产量和设备的可靠性。

公开(公告)号：US08053807B2

公开(公告)日：2011-11-08

申请号：US12923554

申请日：2010-09-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/3121 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2224/03

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

Abstract translation: 半导体封装可以包括半导体图案，接合焊盘和聚合物绝缘构件。 半导体图案可以包括半导体器件和第一孔。 接合焊盘可以包括布线​​图案和插头。 布线图案可以形成在半导体图案的上表面上。 插头可以从布线图案延伸以填充第一孔。 聚合物绝缘构件可以形成在半导体图案的下表面上，并且可以包括暴露插头的下端的第二孔。 制造半导体封装的方法可以包括通过半导体衬底形成第一孔; 形成焊盘和插头; 将支撑构件附接到所述基板的上表面; 减小基板的厚度; 在所述基板的下表面上形成聚合物绝缘部件; 并切割基板。

公开(公告)号：US07825468B2

公开(公告)日：2010-11-02

申请号：US12003544

申请日：2007-12-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L23/04 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2224/03

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

Abstract translation: 半导体封装可以包括半导体图案，接合焊盘和聚合物绝缘构件。 半导体图案可以包括半导体器件和第一孔。 接合焊盘可以包括布线​​图案和插头。 布线图案可以形成在半导体图案的上表面上。 插头可以从布线图案延伸以填充第一孔。 聚合物绝缘构件可以形成在半导体图案的下表面上，并且可以包括暴露插头的下端的第二孔。 制造半导体封装的方法可以包括通过半导体衬底形成第一孔; 形成焊盘和插头; 将支撑构件附接到所述基板的上表面; 减小基板的厚度; 在所述基板的下表面上形成聚合物绝缘部件; 并切割基板。

公开(公告)号：US07732328B2

公开(公告)日：2010-06-08

申请号：US11866942

申请日：2007-10-03

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract translation: 公开了一种半导体封装结构及其制造方法。 制造半导体封装结构的方法可以表征为包括在半导体衬底上形成半导体芯片。 每个半导体芯片包括芯片焊盘。 通孔通过半导体芯片形成。 重新分配结构和芯片选择互连层形成在将通孔与芯片焊盘连接的半导体芯片上。 芯片选择互连层被图案化以在至少一个半导体芯片上形成具有不同结构的芯片选择互连线。 半导体芯片使用贯通孔堆叠并电连接。