公开(公告)号：US08236650B2

公开(公告)日：2012-08-07

申请号：US12686065

申请日：2010-01-12

申请人： Yong-Hoon Son ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘 渠道。

公开(公告)号：US08048784B2

公开(公告)日：2011-11-01

申请号：US12284565

申请日：2008-09-23

申请人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

发明人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/36

CPC分类号： H01L21/02532 ,  H01L21/02636 ,  H01L21/02675

摘要： Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.

摘要翻译： 制造半导体器件的方法包括在衬底上形成含有硅材料的晶种层。 在种子层上形成含有非晶硅材料的非晶硅层。 非晶硅层掺杂有杂质。 将激光束照射到非晶硅层上以产生非晶硅层的相变，并且基于种子层将非晶硅层改变为单晶硅层。

公开(公告)号：US20100112769A1

公开(公告)日：2010-05-06

申请号：US12686065

申请日：2010-01-12

申请人： Yong-Hoon Son ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/8234

CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘 渠道。

公开(公告)号：US20100109079A1

公开(公告)日：2010-05-06

申请号：US12588948

申请日：2009-11-03

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/66666

摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

摘要翻译： 垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。 衬底可分为有源区和隔离层。 可以在对应于有源区的衬底中形成第一杂质区。 通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。 第二杂质区可以形成在沟道图案组的上部。 栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。 栅极绝缘层图案可以与沟道图案组的上表面间隔开。 栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

公开(公告)号：US20100078698A1

公开(公告)日：2010-04-01

申请号：US12585776

申请日：2009-09-24

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

公开(公告)号：US20090242966A1

公开(公告)日：2009-10-01

申请号：US12380565

申请日：2009-02-27

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

摘要翻译： 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

公开(公告)号：US07566602B2

公开(公告)日：2009-07-28

申请号：US11751857

申请日：2007-05-22

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee

IPC分类号： H01L21/84

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/2026 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688

摘要： In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer as a seed for a phase change of the amorphous layer. The laser beam may have an energy for melting the amorphous layer, and the laser beam may be irradiated onto the amorphous layer without generating a superimposedly irradiated region of the amorphous layer. The single crystalline layer may include a high density of large-sized grains without generating a protrusion thereon through a simple process so that a semiconductor device including the single crystalline layer may have a high degree of integration and improved electrical characteristics.

摘要翻译： 在形成单晶半导体层的方法中，可以在包括单晶材料的籽晶层上形成非晶层。 可以通过使用种子层作为非晶层相变的种子将激光束照射到非晶层上，由非晶层形成单晶层。 激光束可以具有用于熔化非晶层的能量，并且可以将激光束照射到非晶层上而不产生非晶层的叠加照射的区域。 单晶层可以包括高密度的大尺寸晶粒，而不通过简单的工艺在其上产生突起，使得包括单晶层的半导体器件可以具有高度集成度和改善的电特性。

公开(公告)号：US07553742B2

公开(公告)日：2009-06-30

申请号：US11329158

申请日：2006-01-11

申请人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee

IPC分类号： H01L21/76

CPC分类号： C30B25/04 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.

摘要翻译： 一种形成薄层的方法，包括提供通过绝缘图案中的开口局部暴露的第一单晶硅层，并在第一单晶硅层上形成外延层，并在绝缘图案上形成非晶硅层， 非晶硅层，其具有与外延层相邻的第一部分和与第一部分间隔开的第二部分，其中非晶硅层在第一部分和第二部分以基本上相同的速率形成在绝缘图案上。 可以将非晶硅层形成为均匀的厚度而没有变薄的缺陷。

公开(公告)号：US20090155971A1

公开(公告)日：2009-06-18

申请号：US12334883

申请日：2008-12-15

申请人： Yong-Hoon Son ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66628 ,  H01L29/7833

摘要： In a semiconductor device and a method of manufacturing the same, a conductive structure is formed on an active region defined by a device isolation layer on a semiconductor substrate. The conductive structure includes a gate pattern and source/drain regions adjacent to the gate pattern. A first semiconductor layer is formed on the active region by a selective epitaxial growth (SEG) process. An amorphous layer is formed on the first semiconductor layer. A second semiconductor layer is formed from a portion of the amorphous layer by a solid-phase epitaxy (SPE) process. Elevated structures are formed on the source/drain regions by removing a remaining portion of the amorphous layer from the substrate so the elevated structure includes the first semiconductor layer and the second semiconductor layer stacked on the first semiconductor layer. The device isolation layer may be prevented from being covered with the elevated structures, to thereby prevent contact failures.

摘要翻译： 在半导体器件及其制造方法中，在由半导体衬底上的器件隔离层限定的有源区上形成导电结构。 导电结构包括栅极图案和与栅极图案相邻的源极/漏极区域。 通过选择性外延生长（SEG）工艺在有源区上形成第一半导体层。 在第一半导体层上形成非晶层。 通过固相外延（SPE）工艺由非晶层的一部分形成第二半导体层。 通过从衬底去除非晶层的剩余部分，在源/漏区上形成升高的结构，因此升高的结构包括堆叠在第一半导体层上的第一半导体层和第二半导体层。 可以防止器件隔离层被升高的结构覆盖，从而防止接触故障。

公开(公告)号：US07470603B2

公开(公告)日：2008-12-30

申请号：US11701694

申请日：2007-02-02

申请人： Yong-Won Cha ,  Sung-Kwan Kang ,  Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

发明人： Yong-Won Cha ,  Sung-Kwan Kang ,  Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02686 ,  H01L29/66651

摘要： Methods of fabricating a semiconductor device are provided. A semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A thin layer is formed on the semiconductor substrate. The thin layer is patterned to form a plurality of spaced apart field structures and to expose therebetween portions of the semiconductor substrate having the single crystalline structure. A non-crystalline layer is formed on the exposed portions of the semiconductor substrate having the single crystalline structure. The non-crystalline layer is planarized to expose upper surfaces of the field structures and define non-crystalline active structures from the non-crystalline layer between the field structures. A laser beam is generated that heats the non-crystalline active structures to change them into single crystalline active structures having substantially the same single crystalline structure as the defined region of the semiconductor substrate.