公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US07205194B2

公开(公告)日：2007-04-17

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20050042828A1

公开(公告)日：2005-02-24

申请号：US10920158

申请日：2004-08-18

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US07375391B2

公开(公告)日：2008-05-20

申请号：US11246590

申请日：2005-10-11

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US20060027858A1

公开(公告)日：2006-02-09

申请号：US11246590

申请日：2005-10-11

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US06974748B2

公开(公告)日：2005-12-13

申请号：US10920158

申请日：2004-08-18

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

公开(公告)号：US20050063208A1

公开(公告)日：2005-03-24

申请号：US10840803

申请日：2004-05-07

申请人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

发明人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

IPC分类号： H01L21/8247 ,  G11C11/42 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

摘要翻译： 提供了使用间隔物氧化工艺制造分裂栅极闪存单元的方法。 在浮栅层上形成氧化阻挡层，在氧化阻挡层中形成露出浮栅的一部分的开口。 随后，通过氧化形成具有绝缘性的材料层的开口的侧壁上的间隔物，并且在开口中形成浮栅和控制栅之间的栅间氧化层图案，同时通过执行 氧化过程。

公开(公告)号：US07115470B2

公开(公告)日：2006-10-03

申请号：US10840803

申请日：2004-05-07

申请人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

发明人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

摘要翻译： 提供了使用间隔物氧化工艺制造分裂栅极闪存单元的方法。 在浮栅层上形成氧化阻挡层，在氧化阻挡层中形成露出浮栅的一部分的开口。 随后，通过氧化形成具有绝缘性的材料层的开口的侧壁上的间隔物，并且在开口中形成浮栅和控制栅之间的栅间氧化层图案，同时通过执行 氧化过程。

公开(公告)号：US20070252190A1

公开(公告)日：2007-11-01

申请号：US11653962

申请日：2007-01-17

申请人： Jae-Hyun Park ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Ji-Woon Rim ,  Young-Cheon Jeong ,  In-Gu Yoon ,  Jung-Ho Moon

发明人： Jae-Hyun Park ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Ji-Woon Rim ,  Young-Cheon Jeong ,  In-Gu Yoon ,  Jung-Ho Moon

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a third insulation layer, a control gate, and a common source line. The semiconductor substrate may have an active region limited by a device isolation region. The floating gate may be formed on the active region with a first insulation layer between the floating gate and the active region. The second insulation layer covers one side of the floating gate, and the third insulation layer covers the floating gate and the second insulation layer. The control gate may be formed on the other side of the floating gate with a fourth insulation layer between the control gate and the floating gate. The common source line may be formed in a portion of the substrate that is located under the second insulation layer.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括半导体衬底，浮置栅极，第二绝缘层，第三绝缘层，控制栅极和公共源极线。 半导体衬底可以具有被器件隔离区限制的有源区。 浮置栅极可以在有源区上形成在浮置栅极和有源区域之间的第一绝缘层。 第二绝缘层覆盖浮栅的一侧，第三绝缘层覆盖浮栅和第二绝缘层。 控制栅极可以在浮动栅极的另一侧上形成在控制栅极和浮动栅极之间的第四绝缘层。 公共源极线可以形成在位于第二绝缘层下方的衬底的一部分中。

公开(公告)号：US20080050875A1

公开(公告)日：2008-02-28

申请号：US11645576

申请日：2006-12-27

申请人： Jung-Ho Moon ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Young-Cheon Jeong ,  In-Gu Yoon ,  Byeong-Cheol Lim

发明人： Jung-Ho Moon ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Young-Cheon Jeong ,  In-Gu Yoon ,  Byeong-Cheol Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11539

摘要： A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.

摘要翻译： 一种复合器件的制造方法包括在包括第一区域和第二区域的半导体衬底上形成第一栅极绝缘图案，在第一栅极绝缘图案上形成第二栅极绝缘层，在形成第二栅极绝缘层之后，形成 在半导体衬底的第二区域中的阱。