公开(公告)号：US20070010068A1

公开(公告)日：2007-01-11

申请号：US11481928

申请日：2006-07-07

申请人： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

发明人： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/32105 ,  H01L21/28273 ,  H01L29/42324

摘要： Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

摘要翻译： 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其它示例实施例涉及制造具有栅电极的半导体器件的方法。 在制造半导体器件的方法中，可以在半导体衬底上形成栅电极。 可以通过自由基再氧化工艺固化或修复半导体衬底和栅电极的侧壁的损伤，以在半导体衬底和栅电极上形成氧化物层。 可以通过在半导体衬底上提供氮气同时将半导体衬底的温度提高到第一温度以在氮气气氛下钝化栅电极的表面来进行自由基再氧化工艺，从而将氧气提供到 半导体衬底，同时将温度从第一温度升至第二温度，以进行第一氧化工艺和/或在第二温度下进行第二氧化工艺。

公开(公告)号：US07592227B2

公开(公告)日：2009-09-22

申请号：US11481928

申请日：2006-07-07

申请人： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

发明人： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/32105 ,  H01L21/28273 ,  H01L29/42324

摘要： Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

摘要翻译： 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其它示例实施例涉及制造具有栅电极的半导体器件的方法。 在制造半导体器件的方法中，可以在半导体衬底上形成栅电极。 可以通过自由基再氧化工艺固化或修复半导体衬底和栅电极的侧壁的损伤，以在半导体衬底和栅电极上形成氧化物层。 可以通过在半导体衬底上提供氮气同时将半导体衬底的温度提高到第一温度以在氮气气氛下钝化栅电极的表面来进行自由基再氧化工艺，从而将氧气提供到 半导体衬底，同时将温度从第一温度升至第二温度，以进行第一氧化工艺和/或在第二温度下进行第二氧化工艺。

公开(公告)号：US20060068547A1

公开(公告)日：2006-03-30

申请号：US11178709

申请日：2005-07-11

申请人： Sang-Hoon Lee ,  Hun-Hyeoung Leam ,  Jai-Dong Lee ,  Jung-Hwan Kim ,  Young-Sub You ,  Ki-Su Na ,  Woong Lee ,  Yong-Sun Lee ,  Won-Jun Jang

发明人： Sang-Hoon Lee ,  Hun-Hyeoung Leam ,  Jai-Dong Lee ,  Jung-Hwan Kim ,  Young-Sub You ,  Ki-Su Na ,  Woong Lee ,  Yong-Sun Lee ,  Won-Jun Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  Y10S438/978

摘要： A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.

摘要翻译： 形成非易失性存储器件的浮置栅极的方法可以包括在衬底上的场隔离图案中蚀刻在场隔离区域之间形成的掩模图案，以将掩模图案的表面凹陷在相邻场隔离区域的上表面之下 以形成具有由表面上方的相邻场隔离区域的侧壁限定的宽度的开口。 然后蚀刻相邻的场隔离区域以增加开口的宽度。

公开(公告)号：US07459364B2

公开(公告)日：2008-12-02

申请号：US11178709

申请日：2005-07-11

申请人： Sang-Hoon Lee ,  Hun-Hyeoung Leam ,  Jai-Dong Lee ,  Jung-Hwan Kim ,  Young-Sub You ,  Ki-Su Na ,  Woong Lee ,  Yong-Sun Lee ,  Won-Jun Jang

发明人： Sang-Hoon Lee ,  Hun-Hyeoung Leam ,  Jai-Dong Lee ,  Jung-Hwan Kim ,  Young-Sub You ,  Ki-Su Na ,  Woong Lee ,  Yong-Sun Lee ,  Won-Jun Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  Y10S438/978

摘要： A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.

摘要翻译： 形成非易失性存储器件的浮置栅极的方法可以包括在衬底上的场隔离图案中蚀刻在场隔离区域之间形成的掩模图案，以将掩模图案的表面凹陷在相邻场隔离区域的上表面之下 以形成具有由表面上方的相邻场隔离区域的侧壁限定的宽度的开口。 然后蚀刻相邻的场隔离区以增加开口的宽度。

公开(公告)号：US20070176225A1

公开(公告)日：2007-08-02

申请号：US11700083

申请日：2007-01-31

申请人： Sang-Hoon Lee ,  Ki-Su Na ,  Man-Sug Kang ,  Yong-Sun Lee ,  Yong-Seok Kim ,  Tae-Jong Lee

发明人： Sang-Hoon Lee ,  Ki-Su Na ,  Man-Sug Kang ,  Yong-Sun Lee ,  Yong-Seok Kim ,  Tae-Jong Lee

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/76224 ,  H01L27/11521

摘要： A semiconductor device having reduced pitting may be formed from isolation layer patterns on a semiconductor substrate defining an active region, a tunnel oxide layer on the active region, the tunnel oxide layer having a nitrified surface, a floating gate on the tunnel oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer.

摘要翻译： 具有减小的点蚀的半导体器件可以由限定有源区的半导体衬底上的隔离层图案，有源区上的隧道氧化物层，具有硝化表面的隧道氧化物层，隧道氧化物层上的浮置栅极， 在浮动栅极上的介电层，以及介电层上的控制栅极。

公开(公告)号：US06974748B2

公开(公告)日：2005-12-13

申请号：US10920158

申请日：2004-08-18

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

公开(公告)号：US20050042828A1

公开(公告)日：2005-02-24

申请号：US10920158

申请日：2004-08-18

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US20100307788A1

公开(公告)日：2010-12-09

申请号：US12867074

申请日：2008-06-26

申请人： Ung Kim ,  Hwa-Joon Lim ,  Yong-Sun Lee ,  Jin-Ho Nam

发明人： Ung Kim ,  Hwa-Joon Lim ,  Yong-Sun Lee ,  Jin-Ho Nam

IPC分类号： H01B9/02 ,  H01B1/24

CPC分类号： C08K5/20 ,  C08K3/04 ,  C08K5/54

摘要： The present invention relates to a peelable and water-crosslinked semiconductive resin composition. The peelable and water-crosslinked semiconductive resin composition includes 100 parts by weight of a basic resin; 20 to 80 parts by weight of carbon black based on weight of the basic resin; and 0.05 to 5.0 parts by weight of an amide-based lubricant based on weight of the basic resin, wherein the basic resin is a mixed resin including 60 to 80 weight % of an ethylene-based copolymer resin that is bonded with an unsaturated organic silane and has a melting point of 80° C. or above; 5 to 20 weight % of an ethylene-acrylic acid copolymer or its alkali metal salt; and 5 to 40 parts by weight of an ethylene propylene copolymer containing 5 to 20 weight % of ethylene, or a propylene rein.

摘要翻译： 本发明涉及一种可剥离和水交联的半导体树脂组合物。 可剥离和水交联的半导体树脂组合物包括100重量份的碱性树脂; 20〜80重量份基于树脂重量的炭黑; 和0.05-5.0重量份基于碱性树脂重量的酰胺类润滑剂，其中所述碱性树脂是包含60-80重量％的与不饱和有机硅烷键合的乙烯类共聚物树脂的混合树脂 并具有80℃以上的熔点; 5〜20重量％的乙烯 - 丙烯酸共聚物或其碱金属盐; 和5至40重量份的含有5至20重量％乙烯或丙烯的乙烯丙烯共聚物。

公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20080182923A1

公开(公告)日：2008-07-31

申请号：US11937191

申请日：2007-11-08

申请人： Do-Hyun Park ,  Jin-Ho Nam ,  Ung Kim ,  Yong-Sun Lee

发明人： Do-Hyun Park ,  Jin-Ho Nam ,  Ung Kim ,  Yong-Sun Lee

IPC分类号： C08K3/00

CPC分类号： C08F255/00 ,  C08F255/02 ,  C08K3/016 ,  C08K5/005 ,  C08K5/02 ,  C08K5/5419 ,  C08L51/06 ,  C09D151/06 ,  C08L2666/02 ,  C08L2666/24

摘要： The present invention relates to a composition for manufacturing insulation materials of an electrical wire and an electrical wire manufactured using the same. The composition for manufacturing insulation materials of an electrical wire according to the present invention includes 100 parts by weight of a base resin, made by blending 20 to 70 weight % of any one resin of an unsaturated organosilane grafted polyethylene and an unsaturated organosilane grafted ethylene alpha olefine copolymer, and 30 to 80 weight % of an unsaturated organosilane grafted ethylene copolymer; 10 to 25 parts by weight of a brominated flame retardant; 10 to 50 parts by weight of an inorganic flame retardant; and 0.2 to 5 parts by weight of compound, as a crosslink retardant, represented as a general formula of XnSi(OR)4-n (X is a phenyl group, R is a methyl group and n is an integer of 1 to 3).

摘要翻译： 本发明涉及一种电线绝缘材料的制造用组合物及使用其制造的电线。 根据本发明的用于制造电线绝缘材料的组合物包括100重量份的基础树脂，其通过将20至70重量％的任何一种不饱和有机硅烷接枝聚乙烯树脂和不饱和有机硅烷接枝的乙烯-α 烯烃共聚物和30〜80重量％的不饱和有机硅烷接枝乙烯共聚物; 10〜25重量份的溴化阻燃剂; 10〜50重量份的无机阻燃剂; 和0.2〜5重量份作为交联剂的化合物，以通式X（OR）4-n表示（X为苯基） R为甲基，n为1〜3的整数）。