公开(公告)号：US06534870B1

公开(公告)日：2003-03-18

申请号：US09594843

申请日：2000-06-15

申请人： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata ,  Rempei Nakata ,  Hideshi Miyajima ,  Motonobu Kawai

发明人： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata ,  Rempei Nakata ,  Hideshi Miyajima ,  Motonobu Kawai

IPC分类号： H01L23485

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Al wirings of first to fifth layers are formed on a P—SiO2 film, and FSG films are formed between the wiring layers. An organic silicon oxide film is formed between wirings in one same wiring layer. The Al wirings in the first and second layers have a carbon concentration of 22 wt %, and the Al wirings in the third to fifth layers have a carbon concentration of 20 wt %.

摘要翻译： 在P-SiO 2膜上形成第一至第五层的Al布线，并且在布线层之间形成FSG膜。 在一个相同的布线层中的布线之间形成有机氧化硅膜。 第一层和第二层的Al配线的碳浓度为22重量％，第三至第五层的Al配线的碳浓度为20重量％。

公开(公告)号：US07745326B2

公开(公告)日：2010-06-29

申请号：US12501901

申请日：2009-07-13

申请人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

发明人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

IPC分类号： H01L21/4763 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

摘要翻译： 一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于布线的多个沟槽，在沟槽中填充金属膜以形成布线，蚀刻第一夹层 将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的沟槽，并且在要填充的沟槽中填充由低介电常数材料制成的第二层间绝缘膜。

公开(公告)号：US07589014B2

公开(公告)日：2009-09-15

申请号：US11565530

申请日：2006-11-30

申请人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

发明人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

摘要翻译： 一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于布线的多个沟槽，在沟槽中填充金属膜以形成布线，蚀刻第一夹层 将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的沟槽，并且在要填充的沟槽中填充由低介电常数材料制成的第二层间绝缘膜。

公开(公告)号：US07855141B2

公开(公告)日：2010-12-21

申请号：US12501839

申请日：2009-07-13

申请人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

发明人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

公开(公告)号：US20070093052A1

公开(公告)日：2007-04-26

申请号：US11565530

申请日：2006-11-30

申请人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

发明人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

摘要翻译： 一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于布线的多个沟槽，在沟槽中填充金属膜以形成布线，蚀刻第一夹层 将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的沟槽，并且在要填充的沟槽中填充由低介电常数材料制成的第二层间绝缘膜。

公开(公告)号：US20090275194A1

公开(公告)日：2009-11-05

申请号：US12501901

申请日：2009-07-13

申请人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

发明人： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

IPC分类号： H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

公开(公告)号：US06781236B2

公开(公告)日：2004-08-24

申请号：US10052259

申请日：2002-01-23

申请人： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata

发明人： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata

IPC分类号： H01L2312

CPC分类号： H01P3/088 ,  H01L23/5222 ,  H01L23/528 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： This invention includes a signal line 17, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate 10, and a differential signal line 13 through which a signal in opposite phase to the signal passing through the signal line passes, or which is connected to a ground power supply, the signal line and the differential signal line are formed so as to be substantially in parallel with each other via an insulating layer 15, and an actual wiring length l of the signal line is longer than a wiring length l0 determined by the following equation l 0 = L C + R 2 + 8 ⁢ π 2 ⁢ f 0 2 ⁢ L 2 4 ⁢ π 2 ⁢ f 0 2 ⁢ C 2 R 2 + 4 ⁢ π 2 ⁢ f 0 2 ⁢ L 2 where R represents a resistance component, L represents an inductance component, and C represents a capacitance component, per unit length of the signal line when no differential signal line exists.

摘要翻译： 本发明包括形成在半导体衬底10上的具有期望频率f0的信号通过的信号线17和与通过信号线的信号相反相位的信号通过的差分信号线13，或 连接到接地电源，信号线和差分信号线经由绝缘层15形成为基本上彼此平行，并且信号线的实际布线长度l比布线长 长度l0由下式确定，其中R表示电阻分量，L表示电感分量，C表示当不存在差分信号线时信号线的每单位长度的电容分量。

公开(公告)号：US06563218B2

公开(公告)日：2003-05-13

申请号：US09995602

申请日：2001-11-29

申请人： Noriaki Matsunaga ,  Yoshiaki Shimooka ,  Kazuyuki Higashi ,  Hideki Shibata

发明人： Noriaki Matsunaga ,  Yoshiaki Shimooka ,  Kazuyuki Higashi ,  Hideki Shibata

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/05556 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

摘要翻译： 多个布线层层压在LSI芯片上。 每个布线层包括施加有机械压力的电极，形成在需要具有高机械强度且其中形成有电极的区域中的第一绝缘膜，形成在与第一绝缘膜相同的层中的第二绝缘膜 形成在不需要比第一绝缘层高的机械强度的区域中的第一绝缘膜的层，以及形成在第二绝缘膜的表面上的布线层。

公开(公告)号：US06750138B2

公开(公告)日：2004-06-15

申请号：US10407426

申请日：2003-04-07

申请人： Noriaki Matsunaga ,  Yoshiaki Shimooka ,  Kazuyuki Higashi ,  Hideki Shibata

发明人： Noriaki Matsunaga ,  Yoshiaki Shimooka ,  Kazuyuki Higashi ,  Hideki Shibata

IPC分类号： H01L214763

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/05556 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

摘要翻译： 多个布线层层压在LSI芯片上。 每个布线层包括施加有机械压力的电极，形成在需要具有高机械强度且其中形成有电极的区域中的第一绝缘膜，形成在与第一绝缘膜相同的层中的第二绝缘膜 形成在不需要比第一绝缘层高的机械强度的区域中的第一绝缘膜的层，以及形成在第二绝缘膜的表面上的布线层。

公开(公告)号：US06291891B1

公开(公告)日：2001-09-18

申请号：US09228642

申请日：1999-01-12

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC分类号： H01L2348

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.